Abstract
In this work, a novel synaptic transistor has been proposed and analyzed through technology computer-aided design (TCAD) simulation. The proposed device has merits of full-Si processing compatibility, short- and long-term plasticity, high energy efficiency, and linear and symmetric conductance adjustability. The proposed device consists of a quantum-well structure and a charge-trap unit for realizing both short- and long-term memories, respectively. The quantum-well charge-trap synaptic transistor (QW CTS) employs two independent gates to separate inference and weight adjustment operation. An optimally designed and validated QW CTS has demonstrated a highly linear and symmetric weight tunability, with an ultra-low energy consumption of 1.5 fJ per synaptic event. The QW CTS can be a core element in the hardware-driven Si neuromorphic system.
| Original language | English |
|---|---|
| Article number | 9146508 |
| Pages (from-to) | 834-840 |
| Number of pages | 7 |
| Journal | IEEE Journal of the Electron Devices Society |
| Volume | 8 |
| DOIs | |
| State | Published - 2020 |
Bibliographical note
Publisher Copyright:© 2013 IEEE.
Keywords
- energy efficiency
- hardware-driven neuromorphic system
- linear weight tunability
- long-term plasticity (LTP)
- quantum-well charge-trap synaptic transistor
- short-term plasticity (STP)
- Si-processing compatibility
