A polycrystalline-silicon dual-gate MOSFET-based 1T-DRAM using grain boundary-induced variable resistance

Young Jun Yoon; Jae Hwa Seo; Seongjae Cho; Jong Ho Lee; In Man Kang

doi:10.1063/1.5090934

A polycrystalline-silicon dual-gate MOSFET-based 1T-DRAM using grain boundary-induced variable resistance

Young Jun Yoon, Jae Hwa Seo, Seongjae Cho, Jong Ho Lee, In Man Kang

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

20 Scopus citations

Abstract

A polycrystalline-silicon (poly-Si) dual-gate MOSFET-based one-transistor dynamic random-access memory (1T-DRAM) cell was developed using grain boundary (GB)-induced barrier effects. The program/erase operation of the 1T-DRAM is performed by trapping/detrapping charges in GB traps. The trapped charges cause variations in the grain energy barrier of the storage region, which forms the sensing margin of the 1T-DRAM. The proposed cell achieved a high sensing margin of 4.45 μA/μm and a long retention time (>100 ms) at a high temperature of 373 K (100 °C).

Original language	English
Article number	183503
Journal	Applied Physics Letters
Volume	114
Issue number	18
DOIs	https://doi.org/10.1063/1.5090934
State	Published - 6 May 2019

Bibliographical note

Funding Information:
This work was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (2016R1C1B2015979); Samsung Electronics Co. Ltd. This work was

Funding Information:
supported by the BK21 Plus project through the NRF funded by the Ministry of Education (21A20131600011). This work was also supported by the Ministry of Trade, Industry & Energy (MOTIE) (10080513) and Korea Semiconductor Research Consortium (KSRC) support program for the development of future semiconductor devices.

Publisher Copyright:
© 2019 Author(s).

Access to Document

10.1063/1.5090934

Cite this

@article{b7cc64f0530746648d800c20ea9dd643,

title = "A polycrystalline-silicon dual-gate MOSFET-based 1T-DRAM using grain boundary-induced variable resistance",

abstract = "A polycrystalline-silicon (poly-Si) dual-gate MOSFET-based one-transistor dynamic random-access memory (1T-DRAM) cell was developed using grain boundary (GB)-induced barrier effects. The program/erase operation of the 1T-DRAM is performed by trapping/detrapping charges in GB traps. The trapped charges cause variations in the grain energy barrier of the storage region, which forms the sensing margin of the 1T-DRAM. The proposed cell achieved a high sensing margin of 4.45 μA/μm and a long retention time (>100 ms) at a high temperature of 373 K (100 °C).",

author = "Yoon, {Young Jun} and Seo, {Jae Hwa} and Seongjae Cho and Lee, {Jong Ho} and Kang, {In Man}",

note = "Funding Information: This work was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (2016R1C1B2015979); Samsung Electronics Co. Ltd. This work was Funding Information: supported by the BK21 Plus project through the NRF funded by the Ministry of Education (21A20131600011). This work was also supported by the Ministry of Trade, Industry & Energy (MOTIE) (10080513) and Korea Semiconductor Research Consortium (KSRC) support program for the development of future semiconductor devices. Publisher Copyright: {\textcopyright} 2019 Author(s).",

year = "2019",

month = may,

day = "6",

doi = "10.1063/1.5090934",

language = "English",

volume = "114",

journal = "Applied Physics Letters",

issn = "0003-6951",

publisher = "American Institute of Physics",

number = "18",

}

TY - JOUR

T1 - A polycrystalline-silicon dual-gate MOSFET-based 1T-DRAM using grain boundary-induced variable resistance

AU - Yoon, Young Jun

AU - Seo, Jae Hwa

AU - Cho, Seongjae

AU - Lee, Jong Ho

AU - Kang, In Man

N1 - Funding Information: This work was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (2016R1C1B2015979); Samsung Electronics Co. Ltd. This work was Funding Information: supported by the BK21 Plus project through the NRF funded by the Ministry of Education (21A20131600011). This work was also supported by the Ministry of Trade, Industry & Energy (MOTIE) (10080513) and Korea Semiconductor Research Consortium (KSRC) support program for the development of future semiconductor devices. Publisher Copyright: © 2019 Author(s).

PY - 2019/5/6

Y1 - 2019/5/6

N2 - A polycrystalline-silicon (poly-Si) dual-gate MOSFET-based one-transistor dynamic random-access memory (1T-DRAM) cell was developed using grain boundary (GB)-induced barrier effects. The program/erase operation of the 1T-DRAM is performed by trapping/detrapping charges in GB traps. The trapped charges cause variations in the grain energy barrier of the storage region, which forms the sensing margin of the 1T-DRAM. The proposed cell achieved a high sensing margin of 4.45 μA/μm and a long retention time (>100 ms) at a high temperature of 373 K (100 °C).

AB - A polycrystalline-silicon (poly-Si) dual-gate MOSFET-based one-transistor dynamic random-access memory (1T-DRAM) cell was developed using grain boundary (GB)-induced barrier effects. The program/erase operation of the 1T-DRAM is performed by trapping/detrapping charges in GB traps. The trapped charges cause variations in the grain energy barrier of the storage region, which forms the sensing margin of the 1T-DRAM. The proposed cell achieved a high sensing margin of 4.45 μA/μm and a long retention time (>100 ms) at a high temperature of 373 K (100 °C).

UR - http://www.scopus.com/inward/record.url?scp=85065521058&partnerID=8YFLogxK

U2 - 10.1063/1.5090934

DO - 10.1063/1.5090934

M3 - Article

AN - SCOPUS:85065521058

SN - 0003-6951

VL - 114

JO - Applied Physics Letters

JF - Applied Physics Letters

IS - 18

M1 - 183503

ER -

A polycrystalline-silicon dual-gate MOSFET-based 1T-DRAM using grain boundary-induced variable resistance

Abstract

Bibliographical note

Access to Document

Fingerprint

Cite this