A polycrystalline-silicon (poly-Si) dual-gate MOSFET-based one-transistor dynamic random-access memory (1T-DRAM) cell was developed using grain boundary (GB)-induced barrier effects. The program/erase operation of the 1T-DRAM is performed by trapping/detrapping charges in GB traps. The trapped charges cause variations in the grain energy barrier of the storage region, which forms the sensing margin of the 1T-DRAM. The proposed cell achieved a high sensing margin of 4.45 μA/μm and a long retention time (>100 ms) at a high temperature of 373 K (100 °C).
Bibliographical noteFunding Information:
This work was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (2016R1C1B2015979); Samsung Electronics Co. Ltd. This work was
supported by the BK21 Plus project through the NRF funded by the Ministry of Education (21A20131600011). This work was also supported by the Ministry of Trade, Industry & Energy (MOTIE) (10080513) and Korea Semiconductor Research Consortium (KSRC) support program for the development of future semiconductor devices.
© 2019 Author(s).