A polycrystalline-silicon dual-gate MOSFET-based 1T-DRAM using grain boundary-induced variable resistance

Young Jun Yoon, Jae Hwa Seo, Seongjae Cho, Jong Ho Lee, In Man Kang

Research output: Contribution to journalArticlepeer-review

21 Scopus citations

Abstract

A polycrystalline-silicon (poly-Si) dual-gate MOSFET-based one-transistor dynamic random-access memory (1T-DRAM) cell was developed using grain boundary (GB)-induced barrier effects. The program/erase operation of the 1T-DRAM is performed by trapping/detrapping charges in GB traps. The trapped charges cause variations in the grain energy barrier of the storage region, which forms the sensing margin of the 1T-DRAM. The proposed cell achieved a high sensing margin of 4.45 μA/μm and a long retention time (>100 ms) at a high temperature of 373 K (100 °C).

Original languageEnglish
Article number183503
JournalApplied Physics Letters
Volume114
Issue number18
DOIs
StatePublished - 6 May 2019

Bibliographical note

Publisher Copyright:
© 2019 Author(s).

Fingerprint

Dive into the research topics of 'A polycrystalline-silicon dual-gate MOSFET-based 1T-DRAM using grain boundary-induced variable resistance'. Together they form a unique fingerprint.

Cite this