A novel TFT with a laterally engineered bandgap for of 3D logic and flash memory

Sung Jin Choi; Jin Woo Han; Sungho Kim; Dong Il Moon; Moongyu Jang; Yang Kyu Choi

doi:10.1109/VLSIT.2010.5556191

A novel TFT with a laterally engineered bandgap for of 3D logic and flash memory

Sung Jin Choi, Jin Woo Han, Sungho Kim, Dong Il Moon, Moongyu Jang, Yang Kyu Choi

Semiconductor Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

26 Scopus citations

Abstract

A dopant segregated Schottky barrier (DSSB) TFT SONOS device is demonstrated for the application of 3D TFT logic devices and flash memory. To apply the DSSB to 3D TFT flash memory, a novel spacer-free structure is successfully implemented. The DSSB TFT SONOS shows a good distribution of programmed V_T by one-time programming with high-speed (a V _T shift of 2.9 V @ 32 ns) due to the use of a unique local injection of carriers from the DSSB S/D junctions and it is not affected by grain boundaries. Moreover, the program speed is accelerated by reduction of the fin width owing to the enhanced field.

Original language	English
Title of host publication	2010 Symposium on VLSI Technology, VLSIT 2010
Pages	111-112
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIT.2010.5556191
State	Published - 2010
Event	2010 Symposium on VLSI Technology, VLSIT 2010 - Honolulu, HI, United States Duration: 15 Jun 2010 → 17 Jun 2010

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Conference

Conference	2010 Symposium on VLSI Technology, VLSIT 2010
Country/Territory	United States
City	Honolulu, HI
Period	15/06/10 → 17/06/10

Access to Document

10.1109/VLSIT.2010.5556191

Cite this

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title = "A novel TFT with a laterally engineered bandgap for of 3D logic and flash memory",

abstract = "A dopant segregated Schottky barrier (DSSB) TFT SONOS device is demonstrated for the application of 3D TFT logic devices and flash memory. To apply the DSSB to 3D TFT flash memory, a novel spacer-free structure is successfully implemented. The DSSB TFT SONOS shows a good distribution of programmed VT by one-time programming with high-speed (a V T shift of 2.9 V @ 32 ns) due to the use of a unique local injection of carriers from the DSSB S/D junctions and it is not affected by grain boundaries. Moreover, the program speed is accelerated by reduction of the fin width owing to the enhanced field.",

author = "Choi, {Sung Jin} and Han, {Jin Woo} and Sungho Kim and Moon, {Dong Il} and Moongyu Jang and Choi, {Yang Kyu}",

year = "2010",

doi = "10.1109/VLSIT.2010.5556191",

language = "English",

isbn = "9781424476374",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

pages = "111--112",

booktitle = "2010 Symposium on VLSI Technology, VLSIT 2010",

note = "2010 Symposium on VLSI Technology, VLSIT 2010 ; Conference date: 15-06-2010 Through 17-06-2010",

}

Choi, SJ, Han, JW, Kim, S, Moon, DI, Jang, M & Choi, YK 2010, A novel TFT with a laterally engineered bandgap for of 3D logic and flash memory. in 2010 Symposium on VLSI Technology, VLSIT 2010., 5556191, Digest of Technical Papers - Symposium on VLSI Technology, pp. 111-112, 2010 Symposium on VLSI Technology, VLSIT 2010, Honolulu, HI, United States, 15/06/10. https://doi.org/10.1109/VLSIT.2010.5556191

A novel TFT with a laterally engineered bandgap for of 3D logic and flash memory. / Choi, Sung Jin; Han, Jin Woo; Kim, Sungho et al.
2010 Symposium on VLSI Technology, VLSIT 2010. 2010. p. 111-112 5556191 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - A dopant segregated Schottky barrier (DSSB) TFT SONOS device is demonstrated for the application of 3D TFT logic devices and flash memory. To apply the DSSB to 3D TFT flash memory, a novel spacer-free structure is successfully implemented. The DSSB TFT SONOS shows a good distribution of programmed VT by one-time programming with high-speed (a V T shift of 2.9 V @ 32 ns) due to the use of a unique local injection of carriers from the DSSB S/D junctions and it is not affected by grain boundaries. Moreover, the program speed is accelerated by reduction of the fin width owing to the enhanced field.

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A novel TFT with a laterally engineered bandgap for of 3D logic and flash memory

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