A novel TFT with a laterally engineered bandgap for of 3D logic and flash memory

Sung Jin Choi, Jin Woo Han, Sungho Kim, Dong Il Moon, Moongyu Jang, Yang Kyu Choi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

26 Scopus citations

Abstract

A dopant segregated Schottky barrier (DSSB) TFT SONOS device is demonstrated for the application of 3D TFT logic devices and flash memory. To apply the DSSB to 3D TFT flash memory, a novel spacer-free structure is successfully implemented. The DSSB TFT SONOS shows a good distribution of programmed VT by one-time programming with high-speed (a V T shift of 2.9 V @ 32 ns) due to the use of a unique local injection of carriers from the DSSB S/D junctions and it is not affected by grain boundaries. Moreover, the program speed is accelerated by reduction of the fin width owing to the enhanced field.

Original languageEnglish
Title of host publication2010 Symposium on VLSI Technology, VLSIT 2010
Pages111-112
Number of pages2
DOIs
StatePublished - 2010
Event2010 Symposium on VLSI Technology, VLSIT 2010 - Honolulu, HI, United States
Duration: 15 Jun 201017 Jun 2010

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Conference

Conference2010 Symposium on VLSI Technology, VLSIT 2010
Country/TerritoryUnited States
CityHonolulu, HI
Period15/06/1017/06/10

Fingerprint

Dive into the research topics of 'A novel TFT with a laterally engineered bandgap for of 3D logic and flash memory'. Together they form a unique fingerprint.

Cite this