A novel 2T0C DRAM architecture using feedback field-effect transistors for reliability improvement

Scaling challenges of conventional one-transistor one-capacitor (1T1C) dynamic random-access memory (DRAM), such as increased refresh power consumption and the manufacturing complexities of high-aspect-ratio capacitors, have highlighted the need for alternative memory architectures. This work introduces a novel two-transistor (2T) DRAM architecture employing a feedback field-effect transistor (FBFET) as the read transistor in the memory cell. By eliminating the need for a charge-storage capacitor, the 2T structure effectively addresses scalability limitations. The positive feedback mechanism instrinsically expected in a FBFET enables a high ON/OFF current ratio, rapid switching, and stable read operations without requiring additional voltage sources. Through a series of Sentaurus technology computer-aided design (TCAD) simulations, the proposed 2T DRAM cell demonstrated significant improvements in retention time, storage node voltage stability, and read current accuracy compared with previous 2T DRAM cells composed of only metal-oxide-semiconductor field-effect transistors (MOSFETs). The influence of critical parameters including write bitline voltage (V_WBL) and channel length (L_CH) have been systematically analyzed. The results show that a shorter channel length enhances the positive feedback, while longer one degrades retention time due to elevation of energy barrier. Furthermore, the impact of the read transistor's gate oxide thickness has also been evaluated. Thicker oxide layers weaken gate control over the channel, leading to faster voltage decay at the storage node (SN) and reduced read current. The proposed 2T DRAM cell design achieves superior data retention, reduced refresh dependency, and enhanced energy efficiency, overcoming the limitations of conventional DRAM cell. These findings underscore the potential of the FBFET-embedded 2T DRAM cell for the next-generation memory applications in the data storage and hardware-oriented artificial intelligence (AI) chips.