TY - GEN
T1 - A Novel 1T DRAM with Shell/Core Dual-Gate Architecture
AU - Ansari, Md Hasan Raza
AU - Cho, Seongjae
N1 - Funding Information:
Read (R) 1.2 -0.1 0.0 0.1 50 20 200 15 102 10 12 14 16 18 20 25 50 75 100 125 0 5 10 15 20 25 RSi (nm) Temperature (°C) WT (ns) Fig. 6. Variation in SM and Tret with Si Fig. 7. Variation in SM and Tret with Fig. 8. Variation of state currents and channel thickness (TSi) of CG device. temperature. SM with WT. 10210REFERENCES2 [1] S. K. Kim et al., MRS Bull., 43, 5, 334–339, 2018. [2] H. N. Khan et al., Nat. Electron., 1, 1, 14–21, 2018. [3] K. Kim, in IEEE VLSI-TSA, 5-9, 2008. [4] www.irds.net IRDS 2018. [5] J. H. Seo et al., IEEE EDL, 40, 4, 566–569, 2019. [6] H. M. Fahad et al., Nano Lett., 11, 10, 4393–4399, 2011. [7] M. H. R. Ansari et al., in IEEE VLSI-TSA, 1–2, 2019. [8] Atlas User’s Manual. Silvaco Int., 2016. [9] M. Vinet et al., IEEE EDL, 26, 5, 317–319, 2005. [10] S.-J. Choi et al., IEEE EDL, 32, 2, 125–127, 2011. with [11] N. Navlakha et al., JAP, 119, 21, 214501, 2016. [12] M. H. R. Ansari et al., IEEE TED, 65, 3, 1205–1210, 2018. [13] N. Navlakha et al., Nanotechnol., 28, 44, 445203, 2017. ACKNOWLEDGEMENT This work was supported by the Ministry of Trade, Industry and Energy (MOTIE) and Korea Semiconductor Research Consortium (KSRC) support program for the development of future semiconductor devices (Grant No. 10080513).
Publisher Copyright:
© 2020 IEEE.
PY - 2020/8
Y1 - 2020/8
N2 - This work proposes for the first time that the core-gate (CG) architectures are utilized as stand-alone and embedded capacitorless (one-transistor, 1T) dynamic random-access memory (DRAM) application with high scalability and strengthened high-temperature operation tolerance. The CG 1T DRAM shows the advantages to increase the effective storage area and conduction regions and better capacitive coupling between the shell and the cores gates due to full depletion (forms deeper potential well for storage) of carriers from the Si film, which achieves better performances compared with double-gate (DG) transistor with same device dimension and biasing scheme. Results indicate that proposed 1T DRAM achieves retention time (Tret) of 3.3 s and 0.95 s at 27 °C and 85 °C, respectively, at gate length (Lg) = 100 nm. The device scalability has been proven down to 10 nm with Tret of 25 ms and sensing margin (SM) of 22.76 μA/μm at 85 °C, which ensures the high potential in the embedded DRAM (eDRAM) applications.
AB - This work proposes for the first time that the core-gate (CG) architectures are utilized as stand-alone and embedded capacitorless (one-transistor, 1T) dynamic random-access memory (DRAM) application with high scalability and strengthened high-temperature operation tolerance. The CG 1T DRAM shows the advantages to increase the effective storage area and conduction regions and better capacitive coupling between the shell and the cores gates due to full depletion (forms deeper potential well for storage) of carriers from the Si film, which achieves better performances compared with double-gate (DG) transistor with same device dimension and biasing scheme. Results indicate that proposed 1T DRAM achieves retention time (Tret) of 3.3 s and 0.95 s at 27 °C and 85 °C, respectively, at gate length (Lg) = 100 nm. The device scalability has been proven down to 10 nm with Tret of 25 ms and sensing margin (SM) of 22.76 μA/μm at 85 °C, which ensures the high potential in the embedded DRAM (eDRAM) applications.
UR - http://www.scopus.com/inward/record.url?scp=85093677299&partnerID=8YFLogxK
U2 - 10.1109/VLSI-TSA48913.2020.9203675
DO - 10.1109/VLSI-TSA48913.2020.9203675
M3 - Conference contribution
AN - SCOPUS:85093677299
T3 - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
SP - 90
EP - 91
BT - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
Y2 - 10 August 2020 through 13 August 2020
ER -