A Novel 1T DRAM with Shell/Core Dual-Gate Architecture

This work proposes for the first time that the core-gate (CG) architectures are utilized as stand-alone and embedded capacitorless (one-transistor, 1T) dynamic random-access memory (DRAM) application with high scalability and strengthened high-temperature operation tolerance. The CG 1T DRAM shows the advantages to increase the effective storage area and conduction regions and better capacitive coupling between the shell and the cores gates due to full depletion (forms deeper potential well for storage) of carriers from the Si film, which achieves better performances compared with double-gate (DG) transistor with same device dimension and biasing scheme. Results indicate that proposed 1T DRAM achieves retention time (Tret) of 3.3 s and 0.95 s at 27 °C and 85 °C, respectively, at gate length (Lg) = 100 nm. The device scalability has been proven down to 10 nm with Tret of 25 ms and sensing margin (SM) of 22.76 μA/μm at 85 °C, which ensures the high potential in the embedded DRAM (eDRAM) applications.