TY - JOUR
T1 - A new structural approach for reducing hot carrier generation in deep submicron MOSFETs
AU - Tasch, Al F.
AU - Shin, Hyungsoon
AU - Maziar, Christine M.
PY - 1990
Y1 - 1990
N2 - A major limitation of the lightly-doped-drain (LDD) type of structure at deep submicron (≤0.35 μm) dimensions is studied and a new structural approach for successfully achieving reliable and manufacturable MOSFETs for L≤0.35 μm is described. The newly reported limit on maximum junction depth and allowable grading of the doping profile of the N-region results from the need to avoid channel doping compensation in order to minimize unacceptable adverse charge-sharing effects. The proposed structural approach overcomes this limitation while suppressing adverse hot-carrier effects. The hot-carrier-suppressed (HCS) MOSFET structure has a lower doped N-region behind a very shallow, steeply profiled N+ source/drain junction. This structural approach should permit MOSFET devices to be more successfully scaled at deep submicron dimensions in terms of performance, reliability, and manufacturability combined.
AB - A major limitation of the lightly-doped-drain (LDD) type of structure at deep submicron (≤0.35 μm) dimensions is studied and a new structural approach for successfully achieving reliable and manufacturable MOSFETs for L≤0.35 μm is described. The newly reported limit on maximum junction depth and allowable grading of the doping profile of the N-region results from the need to avoid channel doping compensation in order to minimize unacceptable adverse charge-sharing effects. The proposed structural approach overcomes this limitation while suppressing adverse hot-carrier effects. The hot-carrier-suppressed (HCS) MOSFET structure has a lower doped N-region behind a very shallow, steeply profiled N+ source/drain junction. This structural approach should permit MOSFET devices to be more successfully scaled at deep submicron dimensions in terms of performance, reliability, and manufacturability combined.
UR - http://www.scopus.com/inward/record.url?scp=0025621994&partnerID=8YFLogxK
U2 - 10.1109/VLSIT.1990.110999
DO - 10.1109/VLSIT.1990.110999
M3 - Conference article
AN - SCOPUS:0025621994
SN - 0743-1562
SP - 43
EP - 44
JO - Digest of Technical Papers - Symposium on VLSI Technology
JF - Digest of Technical Papers - Symposium on VLSI Technology
M1 - 5727459
T2 - 1990 Symposium on VLSI Technology
Y2 - 4 June 1990 through 7 June 1990
ER -