A nanowire transistor for high performance logic and terabit non-volatile memory devices

Hyunjin Lee; Seong Wan Ryu; Jin Woo Han; Lee Eun Yu; Maesoon Im; Chungjin Kim; Sungho Kim; Eujune Lee; Kuk Hwan Kim; Ju Hyun Kim; Dong Il Bae; Sang Cheol Jeon; Kwang Hee Kim; Gi Sung Lee; Jae Suh Oh; Yun Chang Park; Woo Ho Bae; Jung Jae Yoo; Jun Mo Yang; Hee Mok Lee; Yang Kyu Choi

doi:10.1109/VLSIT.2007.4339761

A nanowire transistor for high performance logic and terabit non-volatile memory devices

Hyunjin Lee
, Seong Wan Ryu
, Jin Woo Han
, Lee Eun Yu
, Maesoon Im
, Chungjin Kim
, Sungho Kim
, Eujune Lee
, Kuk Hwan Kim
, Ju Hyun Kim
, Dong Il Bae
, Sang Cheol Jeon
, Kwang Hee Kim
, Gi Sung Lee
, Jae Suh Oh
, Yun Chang Park
, Woo Ho Bae
, Jung Jae Yoo
, Jun Mo Yang
, Hee Mok Lee

Yang Kyu Choi

Semiconductor Engineering

Research output: Contribution to journal › Conference article › peer-review

14 Scopus citations

Abstract

A silicon nanowire-FET (SiNAWI-FET) for high performance logic device with consideration of current direction effects and terabit non-volatile memory (NVM) device using an 8nm SiNAWI-NVM with oxide/nitride/oxide (ONO) and omega-gate structure is reported for the first time. N- and P-channel SiNAWI-FET showed the highest driving current on (110)/〈110〉 crystal orientation without device rotation, whereas most 3-dimensional NMOS report higher driving current on 45° device rotation rather than 0°. Utilizing an 7nm spherical nanowire on the 8nm SiNAWI-NVM with ONO structure, 1.7V V_T-window was achieved from 12V/80μsec program conditions with retention enhancement.

Original language	English
Article number	4339761
Pages (from-to)	144-145
Number of pages	2
Journal	Digest of Technical Papers - Symposium on VLSI Technology
DOIs	https://doi.org/10.1109/VLSIT.2007.4339761
State	Published - 2007
Event	2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan Duration: 12 Jun 2007 → 14 Jun 2007

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Lee, H., Ryu, S. W., Han, J. W., Yu, L. E., Im, M., Kim, C., Kim, S., Lee, E., Kim, K. H., Kim, J. H., Bae, D. I., Jeon, S. C., Kim, K. H., Lee, G. S., Oh, J. S., Park, Y. C., Bae, W. H., Yoo, J. J., Yang, J. M., ... Choi, Y. K. (2007). A nanowire transistor for high performance logic and terabit non-volatile memory devices. Digest of Technical Papers - Symposium on VLSI Technology, 144-145. Article 4339761. https://doi.org/10.1109/VLSIT.2007.4339761

@article{bbba575dcc0c4bf6aa383445b9c89b8e,

title = "A nanowire transistor for high performance logic and terabit non-volatile memory devices",

abstract = "A silicon nanowire-FET (SiNAWI-FET) for high performance logic device with consideration of current direction effects and terabit non-volatile memory (NVM) device using an 8nm SiNAWI-NVM with oxide/nitride/oxide (ONO) and omega-gate structure is reported for the first time. N- and P-channel SiNAWI-FET showed the highest driving current on (110)/〈110〉 crystal orientation without device rotation, whereas most 3-dimensional NMOS report higher driving current on 45° device rotation rather than 0°. Utilizing an 7nm spherical nanowire on the 8nm SiNAWI-NVM with ONO structure, 1.7V VT-window was achieved from 12V/80μsec program conditions with retention enhancement.",

author = "Hyunjin Lee and Ryu, \{Seong Wan\} and Han, \{Jin Woo\} and Yu, \{Lee Eun\} and Maesoon Im and Chungjin Kim and Sungho Kim and Eujune Lee and Kim, \{Kuk Hwan\} and Kim, \{Ju Hyun\} and Bae, \{Dong Il\} and Jeon, \{Sang Cheol\} and Kim, \{Kwang Hee\} and Lee, \{Gi Sung\} and Oh, \{Jae Suh\} and Park, \{Yun Chang\} and Bae, \{Woo Ho\} and Yoo, \{Jung Jae\} and Yang, \{Jun Mo\} and Lee, \{Hee Mok\} and Choi, \{Yang Kyu\}",

year = "2007",

doi = "10.1109/VLSIT.2007.4339761",

language = "English",

pages = "144--145",

journal = "Digest of Technical Papers - Symposium on VLSI Technology",

issn = "0743-1562",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2007 Symposium on VLSI Technology, VLSIT 2007 ; Conference date: 12-06-2007 Through 14-06-2007",

}

Lee, H, Ryu, SW, Han, JW, Yu, LE, Im, M, Kim, C, Kim, S, Lee, E, Kim, KH, Kim, JH, Bae, DI, Jeon, SC, Kim, KH, Lee, GS, Oh, JS, Park, YC, Bae, WH, Yoo, JJ, Yang, JM, Lee, HM & Choi, YK 2007, 'A nanowire transistor for high performance logic and terabit non-volatile memory devices', Digest of Technical Papers - Symposium on VLSI Technology, pp. 144-145. https://doi.org/10.1109/VLSIT.2007.4339761

TY - JOUR

T1 - A nanowire transistor for high performance logic and terabit non-volatile memory devices

AU - Lee, Hyunjin

AU - Ryu, Seong Wan

AU - Han, Jin Woo

AU - Yu, Lee Eun

AU - Im, Maesoon

AU - Kim, Chungjin

AU - Kim, Sungho

AU - Lee, Eujune

AU - Kim, Kuk Hwan

AU - Kim, Ju Hyun

AU - Bae, Dong Il

AU - Jeon, Sang Cheol

AU - Kim, Kwang Hee

AU - Lee, Gi Sung

AU - Oh, Jae Suh

AU - Park, Yun Chang

AU - Bae, Woo Ho

AU - Yoo, Jung Jae

AU - Yang, Jun Mo

AU - Lee, Hee Mok

AU - Choi, Yang Kyu

PY - 2007

Y1 - 2007

N2 - A silicon nanowire-FET (SiNAWI-FET) for high performance logic device with consideration of current direction effects and terabit non-volatile memory (NVM) device using an 8nm SiNAWI-NVM with oxide/nitride/oxide (ONO) and omega-gate structure is reported for the first time. N- and P-channel SiNAWI-FET showed the highest driving current on (110)/〈110〉 crystal orientation without device rotation, whereas most 3-dimensional NMOS report higher driving current on 45° device rotation rather than 0°. Utilizing an 7nm spherical nanowire on the 8nm SiNAWI-NVM with ONO structure, 1.7V VT-window was achieved from 12V/80μsec program conditions with retention enhancement.

AB - A silicon nanowire-FET (SiNAWI-FET) for high performance logic device with consideration of current direction effects and terabit non-volatile memory (NVM) device using an 8nm SiNAWI-NVM with oxide/nitride/oxide (ONO) and omega-gate structure is reported for the first time. N- and P-channel SiNAWI-FET showed the highest driving current on (110)/〈110〉 crystal orientation without device rotation, whereas most 3-dimensional NMOS report higher driving current on 45° device rotation rather than 0°. Utilizing an 7nm spherical nanowire on the 8nm SiNAWI-NVM with ONO structure, 1.7V VT-window was achieved from 12V/80μsec program conditions with retention enhancement.

UR - https://www.scopus.com/pages/publications/43549091463

U2 - 10.1109/VLSIT.2007.4339761

DO - 10.1109/VLSIT.2007.4339761

M3 - Conference article

AN - SCOPUS:43549091463

SN - 0743-1562

SP - 144

EP - 145

JO - Digest of Technical Papers - Symposium on VLSI Technology

JF - Digest of Technical Papers - Symposium on VLSI Technology

M1 - 4339761

T2 - 2007 Symposium on VLSI Technology, VLSIT 2007

Y2 - 12 June 2007 through 14 June 2007

ER -

A nanowire transistor for high performance logic and terabit non-volatile memory devices

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