TY - JOUR
T1 - A low-power gigabit CMOS limiting amplifier using negative impedance compensation and its application
AU - Han, Jungwon
AU - Yoo, Kwisung
AU - Lee, Dongmyung
AU - Park, Kangyeop
AU - Oh, Wonseok
AU - Park, Sung Min
N1 - Funding Information:
Manuscript received August 21, 2010; revised November 25, 2010; accepted December 21, 2010. Date of publication February 14, 2011; date of current version February 17, 2012. This work was supported by the Basic Science Research Program through the National Research Foundation of Korea funded by the Ministry of Education, Science, and Technology under Contract 20100001557.
PY - 2012/3
Y1 - 2012/3
N2 - This paper presents a low-power, gigabit limiting amplifier (LA) for application to optical receivers that employ the negative impedance compensation technique not only to enhance the gain and bandwidth characteristics simultaneously, but also to allow low-voltage, low-power operations. Test chips of the LA were implemented in a standard 0.18-μ m CMOS process, demonstrating 2.5-Gb/s operation with 40-dB gain, 0.053-UI rms jitter for 2 31-1 pseudorandom bit sequence inputs, 9.5-mV pp input sensitivity for 10 - 12 bit error rate (BER), and 5.2-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of only 0.25 × 0.1 mm 2. The proposed LA was adopted to realize a low-power, gigabit optical receiver. Fabricated using the same 0.18-μm CMOS technology, the measured results of the optical receiver chip reveal 132.6-dB Ω transimpedance gain, 2.7-GHz bandwidth even with a large 1.5-pF input parasitic capacitance, -16-dBm optical sensitivity for 10 -12 BER, and 51-mW power dissipation from a single 1.8-V supply. The area of the whole chip is 1.75 × 0.45 mm 2.
AB - This paper presents a low-power, gigabit limiting amplifier (LA) for application to optical receivers that employ the negative impedance compensation technique not only to enhance the gain and bandwidth characteristics simultaneously, but also to allow low-voltage, low-power operations. Test chips of the LA were implemented in a standard 0.18-μ m CMOS process, demonstrating 2.5-Gb/s operation with 40-dB gain, 0.053-UI rms jitter for 2 31-1 pseudorandom bit sequence inputs, 9.5-mV pp input sensitivity for 10 - 12 bit error rate (BER), and 5.2-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of only 0.25 × 0.1 mm 2. The proposed LA was adopted to realize a low-power, gigabit optical receiver. Fabricated using the same 0.18-μm CMOS technology, the measured results of the optical receiver chip reveal 132.6-dB Ω transimpedance gain, 2.7-GHz bandwidth even with a large 1.5-pF input parasitic capacitance, -16-dBm optical sensitivity for 10 -12 BER, and 51-mW power dissipation from a single 1.8-V supply. The area of the whole chip is 1.75 × 0.45 mm 2.
KW - CMOS
KW - DC-balanced transimpedance amplifier
KW - limiting amplifier
KW - negative impedance compensation
KW - optical receivers
UR - http://www.scopus.com/inward/record.url?scp=84857450704&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2010.2104333
DO - 10.1109/TVLSI.2010.2104333
M3 - Article
AN - SCOPUS:84857450704
SN - 1063-8210
VL - 20
SP - 393
EP - 399
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 3
M1 - 5712198
ER -