A Highly Scalable and Energy-Efficient 1T DRAM Embedding a SiGe Quantum Well Structure for Significant Retention Enhancement

Eunseon Yu; Seongjae Cho

doi:10.1109/SISPAD.2018.8551621

A Highly Scalable and Energy-Efficient 1T DRAM Embedding a SiGe Quantum Well Structure for Significant Retention Enhancement

Eunseon Yu, Seongjae Cho

Electronic and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

In this study, a capacitorless one-transistor dynamic random-access memory (1T DRAM) featuring a novel structure with SiGe quantum well (QW) is proposed and characterized by rigorous simulation. It is demonstrated that the ultra-thin vertical channel and SiGe QW greatly improve device scalability and data retention. In write operation, band-to-band tunneling is applied for faster write speed, higher device scalability, and stronger temperature tolerance. Moreover, the SiGe QW at the drain side generates an increased amount of holes at lower operation voltage and enhances the retention time by constructing a more effective hole storage. As the results, the proposed SiGe QW 1T DRAM showed sub-10-ns fast write and erase times and a long retention time reaching up to 1.12 s.

Original language	English
Title of host publication	SISPAD 2018 - 2018 International Conference on Simulation of Semiconductor Processes and Devices, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	255-257
Number of pages	3
ISBN (Electronic)	9781538667880
DOIs	https://doi.org/10.1109/SISPAD.2018.8551621
State	Published - 28 Nov 2018
Event	2018 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2018 - Austin, United States Duration: 24 Sep 2018 → 26 Sep 2018

Publication series

Name	International Conference on Simulation of Semiconductor Processes and Devices, SISPAD
Volume	2018-September

Conference

Conference	2018 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2018
Country/Territory	United States
City	Austin
Period	24/09/18 → 26/09/18

Bibliographical note

Funding Information:
This work was supported by the Ministry of Trade, Industry and Energy (MOTIE) and Korea Semiconductor Research Consortium support program for the development of future semiconductor devices (Grant No. 10080513 and 10052928).

Publisher Copyright:
© 2018 IEEE.

Keywords

1T DRAM
band-to-band tunneling
capacitorless DRAM
enhanced retention time
SiGe quantum well (QW)
SiGe QW 1T DRAM
sub-10-ns write and erase

Access to Document

10.1109/SISPAD.2018.8551621

Cite this

Yu, E., & Cho, S. (2018). A Highly Scalable and Energy-Efficient 1T DRAM Embedding a SiGe Quantum Well Structure for Significant Retention Enhancement. In SISPAD 2018 - 2018 International Conference on Simulation of Semiconductor Processes and Devices, Proceedings (pp. 255-257). Article 8551621 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD; Vol. 2018-September). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SISPAD.2018.8551621

Yu, Eunseon ; Cho, Seongjae. / A Highly Scalable and Energy-Efficient 1T DRAM Embedding a SiGe Quantum Well Structure for Significant Retention Enhancement. SISPAD 2018 - 2018 International Conference on Simulation of Semiconductor Processes and Devices, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 255-257 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD).

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title = "A Highly Scalable and Energy-Efficient 1T DRAM Embedding a SiGe Quantum Well Structure for Significant Retention Enhancement",

abstract = "In this study, a capacitorless one-transistor dynamic random-access memory (1T DRAM) featuring a novel structure with SiGe quantum well (QW) is proposed and characterized by rigorous simulation. It is demonstrated that the ultra-thin vertical channel and SiGe QW greatly improve device scalability and data retention. In write operation, band-to-band tunneling is applied for faster write speed, higher device scalability, and stronger temperature tolerance. Moreover, the SiGe QW at the drain side generates an increased amount of holes at lower operation voltage and enhances the retention time by constructing a more effective hole storage. As the results, the proposed SiGe QW 1T DRAM showed sub-10-ns fast write and erase times and a long retention time reaching up to 1.12 s.",

keywords = "1T DRAM, band-to-band tunneling, capacitorless DRAM, enhanced retention time, SiGe quantum well (QW), SiGe QW 1T DRAM, sub-10-ns write and erase",

author = "Eunseon Yu and Seongjae Cho",

note = "Funding Information: This work was supported by the Ministry of Trade, Industry and Energy (MOTIE) and Korea Semiconductor Research Consortium support program for the development of future semiconductor devices (Grant No. 10080513 and 10052928). Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2018 ; Conference date: 24-09-2018 Through 26-09-2018",

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Yu, E & Cho, S 2018, A Highly Scalable and Energy-Efficient 1T DRAM Embedding a SiGe Quantum Well Structure for Significant Retention Enhancement. in SISPAD 2018 - 2018 International Conference on Simulation of Semiconductor Processes and Devices, Proceedings., 8551621, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, vol. 2018-September, Institute of Electrical and Electronics Engineers Inc., pp. 255-257, 2018 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2018, Austin, United States, 24/09/18. https://doi.org/10.1109/SISPAD.2018.8551621

A Highly Scalable and Energy-Efficient 1T DRAM Embedding a SiGe Quantum Well Structure for Significant Retention Enhancement. / Yu, Eunseon; Cho, Seongjae.
SISPAD 2018 - 2018 International Conference on Simulation of Semiconductor Processes and Devices, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 255-257 8551621 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD; Vol. 2018-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N1 - Funding Information: This work was supported by the Ministry of Trade, Industry and Energy (MOTIE) and Korea Semiconductor Research Consortium support program for the development of future semiconductor devices (Grant No. 10080513 and 10052928). Publisher Copyright: © 2018 IEEE.

PY - 2018/11/28

Y1 - 2018/11/28

N2 - In this study, a capacitorless one-transistor dynamic random-access memory (1T DRAM) featuring a novel structure with SiGe quantum well (QW) is proposed and characterized by rigorous simulation. It is demonstrated that the ultra-thin vertical channel and SiGe QW greatly improve device scalability and data retention. In write operation, band-to-band tunneling is applied for faster write speed, higher device scalability, and stronger temperature tolerance. Moreover, the SiGe QW at the drain side generates an increased amount of holes at lower operation voltage and enhances the retention time by constructing a more effective hole storage. As the results, the proposed SiGe QW 1T DRAM showed sub-10-ns fast write and erase times and a long retention time reaching up to 1.12 s.

AB - In this study, a capacitorless one-transistor dynamic random-access memory (1T DRAM) featuring a novel structure with SiGe quantum well (QW) is proposed and characterized by rigorous simulation. It is demonstrated that the ultra-thin vertical channel and SiGe QW greatly improve device scalability and data retention. In write operation, band-to-band tunneling is applied for faster write speed, higher device scalability, and stronger temperature tolerance. Moreover, the SiGe QW at the drain side generates an increased amount of holes at lower operation voltage and enhances the retention time by constructing a more effective hole storage. As the results, the proposed SiGe QW 1T DRAM showed sub-10-ns fast write and erase times and a long retention time reaching up to 1.12 s.

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Yu E, Cho S. A Highly Scalable and Energy-Efficient 1T DRAM Embedding a SiGe Quantum Well Structure for Significant Retention Enhancement. In SISPAD 2018 - 2018 International Conference on Simulation of Semiconductor Processes and Devices, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. p. 255-257. 8551621. (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD). doi: 10.1109/SISPAD.2018.8551621

A Highly Scalable and Energy-Efficient 1T DRAM Embedding a SiGe Quantum Well Structure for Significant Retention Enhancement

Abstract

Publication series

Conference

Bibliographical note

Keywords

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Cite this