Abstract
In this study, a nonvolatile memory (NVM) device of novel structure in three-dimension is introduced and validated. It is based on a pillar structure where two memory nodes commonly reside. The storage nodes are controlled by a single control gate so that spaces between silicon pillars can be reduced, in which additional gates called cutoff gates realize perfect operations. Gated twin-bit (GTB) NVM device is considered as the ultimate form of 3-D NVM device based on double-gate structure in a sense that the use of common gate makes maximal integration possible. The operation schemes and fabrication method of the GTB NVM device are also introduced.
| Original language | English |
|---|---|
| Article number | 4810110 |
| Pages (from-to) | 595-602 |
| Number of pages | 8 |
| Journal | IEEE Transactions on Nanotechnology |
| Volume | 8 |
| Issue number | 5 |
| DOIs | |
| State | Published - Sep 2009 |
Bibliographical note
Funding Information:Manuscript received July 28, 2008; revised November 12, 2008 and March 4, 2009. First published April 3, 2009; current version published September 4, 2009. This work was supported by Samsung Electronics Corporation and InterUniversity Semiconductor Research Center (ISRC) in Seoul National University (SNU) financially and technically. The review of this paper was arranged by Associate Editor K. Matsumoto.
Keywords
- 3-D nonvolatile memory (NVM) device
- Cutoff gate
- Double-gate structure
- Gated twin-bit (GTB)
- Pillar structure