TY - GEN
T1 - A distributed current stimulator ASIC for high density neural stimulation
AU - Park, Jeong Hoan
AU - Kim, Chaebin
AU - Ahn, Seung Hee
AU - Gwon, Tae Mok
AU - Jeong, Joonsoo
AU - Beom Jun, Sang
AU - Kim, Sung June
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/10/13
Y1 - 2016/10/13
N2 - This paper presents a novel distributed neural stimulator scheme. Instead of a single stimulator ASIC in the package, multiple ASICs are embedded at each electrode site for stimulation with a high density electrode array. This distributed architecture enables the simplification of wiring between electrodes and stimulator ASIC that otherwise could become too complex as the number of electrode increases. The individual ASIC chip is designed to have a shared data bus that independently controls multiple stimulating channels. Therefore, the number of metal lines is determined by the distributed ASICs, not by the channel number. The function of current steering is also implemented within each ASIC in order to increase the effective number of channels via pseudo channel stimulation. Therefore, the chip area can be used more efficiently. The designed chip was fabricated with area of 0.3 mm2 using 0.18 μm BCDMOS process, and the bench-top test was also conducted to validate chip performance.
AB - This paper presents a novel distributed neural stimulator scheme. Instead of a single stimulator ASIC in the package, multiple ASICs are embedded at each electrode site for stimulation with a high density electrode array. This distributed architecture enables the simplification of wiring between electrodes and stimulator ASIC that otherwise could become too complex as the number of electrode increases. The individual ASIC chip is designed to have a shared data bus that independently controls multiple stimulating channels. Therefore, the number of metal lines is determined by the distributed ASICs, not by the channel number. The function of current steering is also implemented within each ASIC in order to increase the effective number of channels via pseudo channel stimulation. Therefore, the chip area can be used more efficiently. The designed chip was fabricated with area of 0.3 mm2 using 0.18 μm BCDMOS process, and the bench-top test was also conducted to validate chip performance.
UR - http://www.scopus.com/inward/record.url?scp=85009145008&partnerID=8YFLogxK
U2 - 10.1109/EMBC.2016.7591060
DO - 10.1109/EMBC.2016.7591060
M3 - Conference contribution
C2 - 28268670
AN - SCOPUS:85009145008
T3 - Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBS
SP - 1770
EP - 1773
BT - 2016 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2016
Y2 - 16 August 2016 through 20 August 2016
ER -