A current-mode CMOS dual-channel 3.5-Gb/s/ch optical receiver array

Xiao Ying; Hanbyul Choi; Seung Hoon Kim; Sung Min Park

doi:10.1109/ISOCC.2013.6864045

A current-mode CMOS dual-channel 3.5-Gb/s/ch optical receiver array

Xiao Ying, Hanbyul Choi, Seung Hoon Kim, Sung Min Park

Electronic and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a dual-channel current-mode optical receiver array which exploits the modified current-mirror(CM) transimpedance amplifiers and the gain-scaling limiting amplifiers. Each modified CM-TIA consists of a CM input configuration with a local feedback, a single-to-differential conversion circuit, a differential amplifier stage, and a 50Ω output buffer. Since the modified CM input effectively isolates the photodiode capacitance from the bandwidth determination, it provides considerable bandwidth enhancement. Also, the gain-scaling limiting amplifiers employ the Cherry-Hooper topology and the capacitive source-degeneration technique to maintain wide bandwidth. Test chips were fabricated by using a standard 0.18-μm CMOS technology, demonstrating 3.5Gb/s operation speed per channel even with 0.52pF total input parasitic capacitance (including 0.32pF photodiode capacitance), and 87mW power dissipation (including output buffer) in total from a single 1.8V supply.

Original language	English
Title of host publication	ISOCC 2013 - 2013 International SoC Design Conference
Publisher	IEEE Computer Society
Pages	343-344
Number of pages	2
ISBN (Print)	9781479911417
DOIs	https://doi.org/10.1109/ISOCC.2013.6864045
State	Published - 2013
Event	2013 International SoC Design Conference, ISOCC 2013 - Busan, Korea, Republic of Duration: 17 Nov 2013 → 19 Nov 2013

Publication series

Name	ISOCC 2013 - 2013 International SoC Design Conference

Conference

Conference	2013 International SoC Design Conference, ISOCC 2013
Country/Territory	Korea, Republic of
City	Busan
Period	17/11/13 → 19/11/13

Keywords

current-mirror
gain-scaling
limiting amplifier
optical receiver array
transimpedance amplifier

Access to Document

10.1109/ISOCC.2013.6864045

Cite this

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title = "A current-mode CMOS dual-channel 3.5-Gb/s/ch optical receiver array",

abstract = "This paper presents a dual-channel current-mode optical receiver array which exploits the modified current-mirror(CM) transimpedance amplifiers and the gain-scaling limiting amplifiers. Each modified CM-TIA consists of a CM input configuration with a local feedback, a single-to-differential conversion circuit, a differential amplifier stage, and a 50Ω output buffer. Since the modified CM input effectively isolates the photodiode capacitance from the bandwidth determination, it provides considerable bandwidth enhancement. Also, the gain-scaling limiting amplifiers employ the Cherry-Hooper topology and the capacitive source-degeneration technique to maintain wide bandwidth. Test chips were fabricated by using a standard 0.18-μm CMOS technology, demonstrating 3.5Gb/s operation speed per channel even with 0.52pF total input parasitic capacitance (including 0.32pF photodiode capacitance), and 87mW power dissipation (including output buffer) in total from a single 1.8V supply.",

keywords = "current-mirror, gain-scaling, limiting amplifier, optical receiver array, transimpedance amplifier",

author = "Xiao Ying and Hanbyul Choi and Kim, {Seung Hoon} and Park, {Sung Min}",

year = "2013",

doi = "10.1109/ISOCC.2013.6864045",

language = "English",

isbn = "9781479911417",

series = "ISOCC 2013 - 2013 International SoC Design Conference",

publisher = "IEEE Computer Society",

pages = "343--344",

booktitle = "ISOCC 2013 - 2013 International SoC Design Conference",

note = "null ; Conference date: 17-11-2013 Through 19-11-2013",

}

Ying, X, Choi, H, Kim, SH & Park, SM 2013, A current-mode CMOS dual-channel 3.5-Gb/s/ch optical receiver array. in ISOCC 2013 - 2013 International SoC Design Conference., 6864045, ISOCC 2013 - 2013 International SoC Design Conference, IEEE Computer Society, pp. 343-344, 2013 International SoC Design Conference, ISOCC 2013, Busan, Korea, Republic of, 17/11/13. https://doi.org/10.1109/ISOCC.2013.6864045

A current-mode CMOS dual-channel 3.5-Gb/s/ch optical receiver array. / Ying, Xiao; Choi, Hanbyul; Kim, Seung Hoon et al.

ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, 2013. p. 343-344 6864045 (ISOCC 2013 - 2013 International SoC Design Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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PY - 2013

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N2 - This paper presents a dual-channel current-mode optical receiver array which exploits the modified current-mirror(CM) transimpedance amplifiers and the gain-scaling limiting amplifiers. Each modified CM-TIA consists of a CM input configuration with a local feedback, a single-to-differential conversion circuit, a differential amplifier stage, and a 50Ω output buffer. Since the modified CM input effectively isolates the photodiode capacitance from the bandwidth determination, it provides considerable bandwidth enhancement. Also, the gain-scaling limiting amplifiers employ the Cherry-Hooper topology and the capacitive source-degeneration technique to maintain wide bandwidth. Test chips were fabricated by using a standard 0.18-μm CMOS technology, demonstrating 3.5Gb/s operation speed per channel even with 0.52pF total input parasitic capacitance (including 0.32pF photodiode capacitance), and 87mW power dissipation (including output buffer) in total from a single 1.8V supply.

AB - This paper presents a dual-channel current-mode optical receiver array which exploits the modified current-mirror(CM) transimpedance amplifiers and the gain-scaling limiting amplifiers. Each modified CM-TIA consists of a CM input configuration with a local feedback, a single-to-differential conversion circuit, a differential amplifier stage, and a 50Ω output buffer. Since the modified CM input effectively isolates the photodiode capacitance from the bandwidth determination, it provides considerable bandwidth enhancement. Also, the gain-scaling limiting amplifiers employ the Cherry-Hooper topology and the capacitive source-degeneration technique to maintain wide bandwidth. Test chips were fabricated by using a standard 0.18-μm CMOS technology, demonstrating 3.5Gb/s operation speed per channel even with 0.52pF total input parasitic capacitance (including 0.32pF photodiode capacitance), and 87mW power dissipation (including output buffer) in total from a single 1.8V supply.

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A current-mode CMOS dual-channel 3.5-Gb/s/ch optical receiver array

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Keywords

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