A current-mode CMOS dual-channel 3.5-Gb/s/ch optical receiver array

This paper presents a dual-channel current-mode optical receiver array which exploits the modified current-mirror(CM) transimpedance amplifiers and the gain-scaling limiting amplifiers. Each modified CM-TIA consists of a CM input configuration with a local feedback, a single-to-differential conversion circuit, a differential amplifier stage, and a 50Ω output buffer. Since the modified CM input effectively isolates the photodiode capacitance from the bandwidth determination, it provides considerable bandwidth enhancement. Also, the gain-scaling limiting amplifiers employ the Cherry-Hooper topology and the capacitive source-degeneration technique to maintain wide bandwidth. Test chips were fabricated by using a standard 0.18-μm CMOS technology, demonstrating 3.5Gb/s operation speed per channel even with 0.52pF total input parasitic capacitance (including 0.32pF photodiode capacitance), and 87mW power dissipation (including output buffer) in total from a single 1.8V supply.