A CMOS symmetric self-biased voltage reference

Minseon Park, Sung Min Park

Research output: Contribution to journalArticlepeer-review

3 Scopus citations


This paper presents a novel CMOS voltage reference circuit named symmetric self-biased voltage reference (SSVR), which enables not only to discard the voltage headroom issue of a conventional constant-gm current source and the inevitable need of an extra bias in a modified constant-gm current source, but also to maintain stable bias voltages with strong tolerance against significant variations of power supply and temperature. Test chips of the SSVR were implemented by using a 0.11-μm CMOS process. Measured results demonstrate that the symmetric configuration of the proposed SSVR helps to achieve constant voltage references against the VDD variation from 0.7 to 1.2 V and the temperature variation from −15 °C to 125 °C. The fabricated chip consumes constant 18.5 μA currents for 0.7 ∼ 1.0-V supply voltages and its core occupies the area of 0.04 × 0.047 mm2.

Original languageEnglish
Pages (from-to)28-33
Number of pages6
JournalMicroelectronics Journal
StatePublished - Oct 2018

Bibliographical note

Publisher Copyright:
© 2018 Elsevier Ltd


  • CMOS
  • Constant-g
  • Modified cascode
  • PVT variation
  • Self-biased
  • Voltage reference


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