A charge trap folded nand flash memory device with band-gap-engineered storage node

Seongjae Cho; Won Bo Shim; Yoon Kim; Jang Gn Yun; Jong Duk Lee; Hyungcheol Shin; Jong Ho Lee; Byung Gook Park

doi:10.1109/TED.2010.2090420

A charge trap folded nand flash memory device with band-gap-engineered storage node

Seongjae Cho, Won Bo Shim, Yoon Kim, Jang Gn Yun, Jong Duk Lee, Hyungcheol Shin, Jong Ho Lee, Byung Gook Park

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

8 Scopus citations

Abstract

A charge trap folded nand (Fnand ) Flash memory device with band-gap-engineered (BE) storage node is proposed. Because of the compact cell layout without junction contacts, a nand Flash memory is the most suitable memory medium for electronic appliances. Two memory cells are put together to have a common vertical channel, which enables one to achieve a theoretical near-30-nm technology. The resulting array is made by folding the conventional 2-D Flash memory and is called Fnand. The memory storage node uses a BE stack structure, where the oxidenitrideoxide multilayers replace the tunnel oxide. The fin structures for both wordline and bitline have been formed by sidewall spacer patterning, instead of photolithography. The fabrication processes for SONONOS nand Flash memory having independent double gates are explained. Electrical characteristics regarding memory operations under paired cell interference are analyzed.

Original language	English
Article number	5643136
Pages (from-to)	288-295
Number of pages	8
Journal	IEEE Transactions on Electron Devices
Volume	58
Issue number	2
DOIs	https://doi.org/10.1109/TED.2010.2090420
State	Published - Feb 2011

Bibliographical note

Funding Information:
Manuscript received March 22, 2010; revised October 19, 2010; accepted October 19, 2010. Date of publication November 22, 2010; date of current version January 21, 2011. This work was supported in part by Samsung Electronics Corporation, by the Inter-university Semiconductor Research Center, and by the Brain Korea 21 program of Seoul National University. The review of this paper was arranged by Editor H. Jaouen.

Keywords

Band-gap engineering
charge trap
double gate
flash memory
folded nand (F nand)
paired cell interference (PCI)
sidewall spacer patterning

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10.1109/TED.2010.2090420

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title = "A charge trap folded nand flash memory device with band-gap-engineered storage node",

abstract = "A charge trap folded nand (Fnand ) Flash memory device with band-gap-engineered (BE) storage node is proposed. Because of the compact cell layout without junction contacts, a nand Flash memory is the most suitable memory medium for electronic appliances. Two memory cells are put together to have a common vertical channel, which enables one to achieve a theoretical near-30-nm technology. The resulting array is made by folding the conventional 2-D Flash memory and is called Fnand. The memory storage node uses a BE stack structure, where the oxidenitrideoxide multilayers replace the tunnel oxide. The fin structures for both wordline and bitline have been formed by sidewall spacer patterning, instead of photolithography. The fabrication processes for SONONOS nand Flash memory having independent double gates are explained. Electrical characteristics regarding memory operations under paired cell interference are analyzed.",

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note = "Funding Information: Manuscript received March 22, 2010; revised October 19, 2010; accepted October 19, 2010. Date of publication November 22, 2010; date of current version January 21, 2011. This work was supported in part by Samsung Electronics Corporation, by the Inter-university Semiconductor Research Center, and by the Brain Korea 21 program of Seoul National University. The review of this paper was arranged by Editor H. Jaouen.",

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AU - Shin, Hyungcheol

AU - Lee, Jong Ho

AU - Park, Byung Gook

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A charge trap folded nand flash memory device with band-gap-engineered storage node

Abstract

Bibliographical note

Keywords

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