A band-engineered one-transistor DRAM with improved data retention and power efficiency

Eunseon Yu; Seongjae Cho; Hyungsoon Shin; Byung Gook Park

doi:10.1109/LED.2019.2902334

A band-engineered one-transistor DRAM with improved data retention and power efficiency

Eunseon Yu, Seongjae Cho, Hyungsoon Shin, Byung Gook Park

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

19 Scopus citations

Abstract

In this letter, a one-transistor (1T) dynamic random-access memory (DRAM) with SiGe quantum well (QW) is proposed, and its performance is validated through the technology computer-aided design (TCAD) simulation. At the write operation, band-to-band tunneling is used and 1 V or lower programming voltage is realized by inserting the SiGe QW beside the drain. This QW also functions as the storage node, which enhances not only the current sensing margin but also the retention time (τ_ret) compared with those of all-Si device. At an extremely scaled cell size and sub-10-ns write/erase operations, the proposed device shows 0.2-s-long τ_ret and current ratio > 10⁴. It has been verified that a single cycle of 1T DRAM operations consumes only 93.8 fJ.

Original language	English
Article number	8654635
Pages (from-to)	562-565
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	40
Issue number	4
DOIs	https://doi.org/10.1109/LED.2019.2902334
State	Published - Apr 2019

Bibliographical note

Publisher Copyright:
© 1980-2012 IEEE.

Keywords

DRAM retention
One-transistor DRAM
SiGe quantum well
band-to-band tunneling
low-power operation

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10.1109/LED.2019.2902334

Cite this

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abstract = "In this letter, a one-transistor (1T) dynamic random-access memory (DRAM) with SiGe quantum well (QW) is proposed, and its performance is validated through the technology computer-aided design (TCAD) simulation. At the write operation, band-to-band tunneling is used and 1 V or lower programming voltage is realized by inserting the SiGe QW beside the drain. This QW also functions as the storage node, which enhances not only the current sensing margin but also the retention time (τret) compared with those of all-Si device. At an extremely scaled cell size and sub-10-ns write/erase operations, the proposed device shows 0.2-s-long τret and current ratio > 104. It has been verified that a single cycle of 1T DRAM operations consumes only 93.8 fJ.",

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A band-engineered one-transistor DRAM with improved data retention and power efficiency

Abstract

Bibliographical note

Keywords

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