A 9-72 V Input to 1-2.2V Output Single-Inductor Multipath Multi-Stage Hybrid Dc-Dc Converter Achieving 87.8% Peak Efficiency with 110m Ω DCR Inductor

Geuntae Park; Yuli Han; Seongil Yeo; Jusung Kim; Kunhee Cho

doi:10.1109/ESSERC66193.2025.11213980

A 9-72 V Input to 1-2.2V Output Single-Inductor Multipath Multi-Stage Hybrid Dc-Dc Converter Achieving 87.8% Peak Efficiency with 110m Ω DCR Inductor

Geuntae Park
, Yuli Han
, Seongil Yeo
, Jusung Kim
, Kunhee Cho

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a single-inductor multi-path multi-stage (MPMS) hybrid DC-DC converter designed for ultra-low voltage conversion ratio (VCR) operation. A design methodology for the inductor-middle hybrid converter architecture is introduced, and an optimized switched-capacitor (SC)-based hybrid converter for both the first and second stages, combined with the proposed multi-path (MP) design, is demonstrated. The MP architecture effectively reduces inductor RMS current and voltage stress on the switches, minimizing losses across a wide V_IN range. A start-up control using only internal switches is also employed to pre-charge both the flying and output capacitors appropriately. The proposed MPMS hybrid converter is fabricated in a 0.18 μ m BCDMOS process and supports a Vin range of 9V-72 V and a Vout range of 1 V 2.2 V. A peak efficiency of 87.8% is achieved using a compact inductor with a 110 m Ω DCR.

Original language	English
Title of host publication	Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025
Publisher	IEEE Computer Society
Pages	193-196
Number of pages	4
ISBN (Electronic)	9798331525392
DOIs	https://doi.org/10.1109/ESSERC66193.2025.11213980
State	Published - 2025
Event	51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025 - Munich, Germany Duration: 8 Sep 2025 → 11 Sep 2025

Publication series

Name	European Solid-State Circuits Conference
ISSN (Print)	1930-8833

Conference

Conference	51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025
Country/Territory	Germany
City	Munich
Period	8/09/25 → 11/09/25

Bibliographical note

Publisher Copyright:
© 2025 IEEE.

Keywords

Hybrid DC-DC converter
inductor-middle DC-DC converter
multi-path multistage
soft-start
ultra-low voltage conversion ratio
wide input voltage range

Access to Document

10.1109/ESSERC66193.2025.11213980

Cite this

Park, G., Han, Y., Yeo, S., Kim, J., & Cho, K. (2025). A 9-72 V Input to 1-2.2V Output Single-Inductor Multipath Multi-Stage Hybrid Dc-Dc Converter Achieving 87.8% Peak Efficiency with 110m Ω DCR Inductor. In Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025 (pp. 193-196). (European Solid-State Circuits Conference). IEEE Computer Society. https://doi.org/10.1109/ESSERC66193.2025.11213980

Park, Geuntae ; Han, Yuli ; Yeo, Seongil et al. / A 9-72 V Input to 1-2.2V Output Single-Inductor Multipath Multi-Stage Hybrid Dc-Dc Converter Achieving 87.8% Peak Efficiency with 110m Ω DCR Inductor. Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025. IEEE Computer Society, 2025. pp. 193-196 (European Solid-State Circuits Conference).

@inproceedings{c3593c4f5862415986b78f69a3f6f0a8,

title = "A 9-72 V Input to 1-2.2V Output Single-Inductor Multipath Multi-Stage Hybrid Dc-Dc Converter Achieving 87.8\% Peak Efficiency with 110m Ω DCR Inductor",

abstract = "This paper presents a single-inductor multi-path multi-stage (MPMS) hybrid DC-DC converter designed for ultra-low voltage conversion ratio (VCR) operation. A design methodology for the inductor-middle hybrid converter architecture is introduced, and an optimized switched-capacitor (SC)-based hybrid converter for both the first and second stages, combined with the proposed multi-path (MP) design, is demonstrated. The MP architecture effectively reduces inductor RMS current and voltage stress on the switches, minimizing losses across a wide VIN range. A start-up control using only internal switches is also employed to pre-charge both the flying and output capacitors appropriately. The proposed MPMS hybrid converter is fabricated in a 0.18 μ m BCDMOS process and supports a Vin range of 9V-72 V and a Vout range of 1 V 2.2 V. A peak efficiency of 87.8\% is achieved using a compact inductor with a 110 m Ω DCR.",

keywords = "Hybrid DC-DC converter, inductor-middle DC-DC converter, multi-path multistage, soft-start, ultra-low voltage conversion ratio, wide input voltage range",

author = "Geuntae Park and Yuli Han and Seongil Yeo and Jusung Kim and Kunhee Cho",

note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025 ; Conference date: 08-09-2025 Through 11-09-2025",

year = "2025",

doi = "10.1109/ESSERC66193.2025.11213980",

language = "English",

series = "European Solid-State Circuits Conference",

publisher = "IEEE Computer Society",

pages = "193--196",

booktitle = "Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025",

}

Park, G, Han, Y, Yeo, S, Kim, J & Cho, K 2025, A 9-72 V Input to 1-2.2V Output Single-Inductor Multipath Multi-Stage Hybrid Dc-Dc Converter Achieving 87.8% Peak Efficiency with 110m Ω DCR Inductor. in Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025. European Solid-State Circuits Conference, IEEE Computer Society, pp. 193-196, 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025, Munich, Germany, 8/09/25. https://doi.org/10.1109/ESSERC66193.2025.11213980

A 9-72 V Input to 1-2.2V Output Single-Inductor Multipath Multi-Stage Hybrid Dc-Dc Converter Achieving 87.8% Peak Efficiency with 110m Ω DCR Inductor. / Park, Geuntae; Han, Yuli; Yeo, Seongil et al.
Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025. IEEE Computer Society, 2025. p. 193-196 (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 9-72 V Input to 1-2.2V Output Single-Inductor Multipath Multi-Stage Hybrid Dc-Dc Converter Achieving 87.8% Peak Efficiency with 110m Ω DCR Inductor

AU - Park, Geuntae

AU - Han, Yuli

AU - Yeo, Seongil

AU - Kim, Jusung

AU - Cho, Kunhee

PY - 2025

Y1 - 2025

N2 - This paper presents a single-inductor multi-path multi-stage (MPMS) hybrid DC-DC converter designed for ultra-low voltage conversion ratio (VCR) operation. A design methodology for the inductor-middle hybrid converter architecture is introduced, and an optimized switched-capacitor (SC)-based hybrid converter for both the first and second stages, combined with the proposed multi-path (MP) design, is demonstrated. The MP architecture effectively reduces inductor RMS current and voltage stress on the switches, minimizing losses across a wide VIN range. A start-up control using only internal switches is also employed to pre-charge both the flying and output capacitors appropriately. The proposed MPMS hybrid converter is fabricated in a 0.18 μ m BCDMOS process and supports a Vin range of 9V-72 V and a Vout range of 1 V 2.2 V. A peak efficiency of 87.8% is achieved using a compact inductor with a 110 m Ω DCR.

AB - This paper presents a single-inductor multi-path multi-stage (MPMS) hybrid DC-DC converter designed for ultra-low voltage conversion ratio (VCR) operation. A design methodology for the inductor-middle hybrid converter architecture is introduced, and an optimized switched-capacitor (SC)-based hybrid converter for both the first and second stages, combined with the proposed multi-path (MP) design, is demonstrated. The MP architecture effectively reduces inductor RMS current and voltage stress on the switches, minimizing losses across a wide VIN range. A start-up control using only internal switches is also employed to pre-charge both the flying and output capacitors appropriately. The proposed MPMS hybrid converter is fabricated in a 0.18 μ m BCDMOS process and supports a Vin range of 9V-72 V and a Vout range of 1 V 2.2 V. A peak efficiency of 87.8% is achieved using a compact inductor with a 110 m Ω DCR.

KW - Hybrid DC-DC converter

KW - inductor-middle DC-DC converter

KW - multi-path multistage

KW - soft-start

KW - ultra-low voltage conversion ratio

KW - wide input voltage range

UR - https://www.scopus.com/pages/publications/105024554622

U2 - 10.1109/ESSERC66193.2025.11213980

DO - 10.1109/ESSERC66193.2025.11213980

M3 - Conference contribution

AN - SCOPUS:105024554622

T3 - European Solid-State Circuits Conference

SP - 193

EP - 196

BT - Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025

PB - IEEE Computer Society

T2 - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025

Y2 - 8 September 2025 through 11 September 2025

ER -

Park G, Han Y, Yeo S, Kim J, Cho K. A 9-72 V Input to 1-2.2V Output Single-Inductor Multipath Multi-Stage Hybrid Dc-Dc Converter Achieving 87.8% Peak Efficiency with 110m Ω DCR Inductor. In Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025. IEEE Computer Society. 2025. p. 193-196. (European Solid-State Circuits Conference). doi: 10.1109/ESSERC66193.2025.11213980

A 9-72 V Input to 1-2.2V Output Single-Inductor Multipath Multi-Stage Hybrid Dc-Dc Converter Achieving 87.8% Peak Efficiency with 110m Ω DCR Inductor

Abstract

Publication series

Conference

Bibliographical note

Keywords

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Cite this