A 6.6 mW, -94 dBc/Hz, 1.0-to-4.5 GHz phase-lock loop in 65-nm CMOS

Kyungmin Lee, Chaerin Hong, He Ying, Dayoung Kim, Seung Hoon Kim, Sung Min Park

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

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