A 6.6 mW, -94 dBc/Hz, 1.0-to-4.5 GHz phase-lock loop in 65-nm CMOS

Kyungmin Lee; Chaerin Hong; He Ying; Dayoung Kim; Seung Hoon Kim; Sung Min Park

doi:10.1109/ISOCC.2015.7401734

A 6.6 mW, -94 dBc/Hz, 1.0-to-4.5 GHz phase-lock loop in 65-nm CMOS

Kyungmin Lee, Chaerin Hong, He Ying, Dayoung Kim, Seung Hoon Kim, Sung Min Park

Electronic and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This paper presents a phase-lock loop (PLL) realized in a standard 65-nm CMOS technology, which multiplies a 50-MHz reference to generate 1.0∼4.5 GHz clock signals. The proposed PLL consists of a PFD, a charge pump, a 3rd-order LPF, a ring VCO, a 2/3 prescaler, and a 6-bit divider, providing low cost, small area, and wide tuning characteristics. Post-layout simulations reveal that the PLL achieves 1.0∼4.5 GHz tuning range, -94-dBc/Hz phase noise at 3 GHz with 1-MHz offset, and 6.6-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of 99 × 106 p.m2.

Original language	English
Title of host publication	ISOCC 2015 - International SoC Design Conference
Subtitle of host publication	SoC for Internet of Everything (IoE)
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	235-236
Number of pages	2
ISBN (Electronic)	9781467393089
DOIs	https://doi.org/10.1109/ISOCC.2015.7401734
State	Published - 8 Feb 2016
Event	12th International SoC Design Conference, ISOCC 2015 - Gyeongju, Korea, Republic of Duration: 2 Nov 2015 → 5 Nov 2015

Publication series

Name	ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)

Conference

Conference	12th International SoC Design Conference, ISOCC 2015
Country/Territory	Korea, Republic of
City	Gyeongju
Period	2/11/15 → 5/11/15

Keywords

CMOS
PLL
frequency synthesizer
ring VCO
tuning range

Access to Document

10.1109/ISOCC.2015.7401734

Cite this

Lee, K., Hong, C., Ying, H., Kim, D., Kim, S. H., & Park, S. M. (2016). A 6.6 mW, -94 dBc/Hz, 1.0-to-4.5 GHz phase-lock loop in 65-nm CMOS. In ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE) (pp. 235-236). [7401734] (ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2015.7401734

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title = "A 6.6 mW, -94 dBc/Hz, 1.0-to-4.5 GHz phase-lock loop in 65-nm CMOS",

abstract = "This paper presents a phase-lock loop (PLL) realized in a standard 65-nm CMOS technology, which multiplies a 50-MHz reference to generate 1.0∼4.5 GHz clock signals. The proposed PLL consists of a PFD, a charge pump, a 3rd-order LPF, a ring VCO, a 2/3 prescaler, and a 6-bit divider, providing low cost, small area, and wide tuning characteristics. Post-layout simulations reveal that the PLL achieves 1.0∼4.5 GHz tuning range, -94-dBc/Hz phase noise at 3 GHz with 1-MHz offset, and 6.6-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of 99 × 106 p.m2.",

keywords = "CMOS, PLL, frequency synthesizer, ring VCO, tuning range",

author = "Kyungmin Lee and Chaerin Hong and He Ying and Dayoung Kim and Kim, {Seung Hoon} and Park, {Sung Min}",

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Lee, K, Hong, C, Ying, H, Kim, D, Kim, SH & Park, SM 2016, A 6.6 mW, -94 dBc/Hz, 1.0-to-4.5 GHz phase-lock loop in 65-nm CMOS. in ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)., 7401734, ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE), Institute of Electrical and Electronics Engineers Inc., pp. 235-236, 12th International SoC Design Conference, ISOCC 2015, Gyeongju, Korea, Republic of, 2/11/15. https://doi.org/10.1109/ISOCC.2015.7401734

A 6.6 mW, -94 dBc/Hz, 1.0-to-4.5 GHz phase-lock loop in 65-nm CMOS. / Lee, Kyungmin; Hong, Chaerin; Ying, He et al.

ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc., 2016. p. 235-236 7401734 (ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - A 6.6 mW, -94 dBc/Hz, 1.0-to-4.5 GHz phase-lock loop in 65-nm CMOS

AU - Lee, Kyungmin

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AB - This paper presents a phase-lock loop (PLL) realized in a standard 65-nm CMOS technology, which multiplies a 50-MHz reference to generate 1.0∼4.5 GHz clock signals. The proposed PLL consists of a PFD, a charge pump, a 3rd-order LPF, a ring VCO, a 2/3 prescaler, and a 6-bit divider, providing low cost, small area, and wide tuning characteristics. Post-layout simulations reveal that the PLL achieves 1.0∼4.5 GHz tuning range, -94-dBc/Hz phase noise at 3 GHz with 1-MHz offset, and 6.6-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of 99 × 106 p.m2.

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Lee K, Hong C, Ying H, Kim D, Kim SH, Park SM. A 6.6 mW, -94 dBc/Hz, 1.0-to-4.5 GHz phase-lock loop in 65-nm CMOS. In ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc. 2016. p. 235-236. 7401734. (ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)). doi: 10.1109/ISOCC.2015.7401734

A 6.6 mW, -94 dBc/Hz, 1.0-to-4.5 GHz phase-lock loop in 65-nm CMOS

Abstract

Publication series

Conference

Keywords

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