TY - GEN
T1 - A 6.6 mW, -94 dBc/Hz, 1.0-to-4.5 GHz phase-lock loop in 65-nm CMOS
AU - Lee, Kyungmin
AU - Hong, Chaerin
AU - Ying, He
AU - Kim, Dayoung
AU - Kim, Seung Hoon
AU - Park, Sung Min
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2016/2/8
Y1 - 2016/2/8
N2 - This paper presents a phase-lock loop (PLL) realized in a standard 65-nm CMOS technology, which multiplies a 50-MHz reference to generate 1.0∼4.5 GHz clock signals. The proposed PLL consists of a PFD, a charge pump, a 3rd-order LPF, a ring VCO, a 2/3 prescaler, and a 6-bit divider, providing low cost, small area, and wide tuning characteristics. Post-layout simulations reveal that the PLL achieves 1.0∼4.5 GHz tuning range, -94-dBc/Hz phase noise at 3 GHz with 1-MHz offset, and 6.6-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of 99 × 106 p.m2.
AB - This paper presents a phase-lock loop (PLL) realized in a standard 65-nm CMOS technology, which multiplies a 50-MHz reference to generate 1.0∼4.5 GHz clock signals. The proposed PLL consists of a PFD, a charge pump, a 3rd-order LPF, a ring VCO, a 2/3 prescaler, and a 6-bit divider, providing low cost, small area, and wide tuning characteristics. Post-layout simulations reveal that the PLL achieves 1.0∼4.5 GHz tuning range, -94-dBc/Hz phase noise at 3 GHz with 1-MHz offset, and 6.6-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of 99 × 106 p.m2.
KW - CMOS
KW - PLL
KW - frequency synthesizer
KW - ring VCO
KW - tuning range
UR - http://www.scopus.com/inward/record.url?scp=84963865336&partnerID=8YFLogxK
U2 - 10.1109/ISOCC.2015.7401734
DO - 10.1109/ISOCC.2015.7401734
M3 - Conference contribution
AN - SCOPUS:84963865336
T3 - ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)
SP - 235
EP - 236
BT - ISOCC 2015 - International SoC Design Conference
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 2 November 2015 through 5 November 2015
ER -