A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology

Sang Gyun Kim, Seung Hwan Jung, Yun Seong Eo, Seung Hoon Kim, Xiao Ying, Hanbyul Choi, Chaerin Hong, Kyungmin Lee, Sung Min Park

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

16 Scopus citations

Abstract

A 50-Gb/s differential transimpedance amplifier is realized in a standard 65nm CMOS process, which exploits asymmetric transformer peaking technique for bandwidth extension and employs a modified regulated-cascode input stage with a shunt-feedback common-source amplifier for differential signaling. Measured results demonstrate 52-dBΩ transimpedance gain, 50-GHz bandwidth for 50fF photodiode capacitance, -12.3dBm sensitivity for 10-12 BER, and 49.2-mW power dissipation from a single 1.2-V supply. To the best of authors' knowledge, this chip achieves the fastest operation speed among the recently reported gigabit CMOS transimpedance amplifiers. The chip occupies the total area of 1.2×0.8mm2 including pad.

Original languageEnglish
Title of host publication2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages357-360
Number of pages4
ISBN (Electronic)9781479940905
DOIs
StatePublished - 13 Jan 2015
Event2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 - Kaohsiung, Taiwan, Province of China
Duration: 10 Nov 201412 Nov 2014

Publication series

Name2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers

Conference

Conference2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014
Country/TerritoryTaiwan, Province of China
CityKaohsiung
Period10/11/1412/11/14

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

Keywords

  • CMOS
  • TIA
  • regulated-cascode
  • transformer

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