A 50-Gb/s differential transimpedance amplifier is realized in a standard 65nm CMOS process, which exploits asymmetric transformer peaking technique for bandwidth extension and employs a modified regulated-cascode input stage with a shunt-feedback common-source amplifier for differential signaling. Measured results demonstrate 52-dBΩ transimpedance gain, 50-GHz bandwidth for 50fF photodiode capacitance, -12.3dBm sensitivity for 10-12 BER, and 49.2-mW power dissipation from a single 1.2-V supply. To the best of authors' knowledge, this chip achieves the fastest operation speed among the recently reported gigabit CMOS transimpedance amplifiers. The chip occupies the total area of 1.2×0.8mm2 including pad.
|Title of host publication||2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|State||Published - 13 Jan 2015|
|Event||2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 - Kaohsiung, Taiwan, Province of China|
Duration: 10 Nov 2014 → 12 Nov 2014
|Name||2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers|
|Conference||2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014|
|Country/Territory||Taiwan, Province of China|
|Period||10/11/14 → 12/11/14|
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© 2014 IEEE.