@inproceedings{cdcc7936b63448b087a4e1133c801050,
title = "A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology",
abstract = "A 50-Gb/s differential transimpedance amplifier is realized in a standard 65nm CMOS process, which exploits asymmetric transformer peaking technique for bandwidth extension and employs a modified regulated-cascode input stage with a shunt-feedback common-source amplifier for differential signaling. Measured results demonstrate 52-dBΩ transimpedance gain, 50-GHz bandwidth for 50fF photodiode capacitance, -12.3dBm sensitivity for 10-12 BER, and 49.2-mW power dissipation from a single 1.2-V supply. To the best of authors' knowledge, this chip achieves the fastest operation speed among the recently reported gigabit CMOS transimpedance amplifiers. The chip occupies the total area of 1.2×0.8mm2 including pad.",
keywords = "CMOS, regulated-cascode, TIA, transformer",
author = "Kim, {Sang Gyun} and Jung, {Seung Hwan} and Eo, {Yun Seong} and Kim, {Seung Hoon} and Xiao Ying and Hanbyul Choi and Chaerin Hong and Kyungmin Lee and Park, {Sung Min}",
note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 ; Conference date: 10-11-2014 Through 12-11-2014",
year = "2015",
month = jan,
day = "13",
doi = "10.1109/ASSCC.2014.7008934",
language = "English",
series = "2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "357--360",
booktitle = "2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers",
}