A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology

Sang Gyun Kim; Seung Hwan Jung; Yun Seong Eo; Seung Hoon Kim; Xiao Ying; Hanbyul Choi; Chaerin Hong; Kyungmin Lee; Sung Min Park

doi:10.1109/ASSCC.2014.7008934

A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology

Sang Gyun Kim, Seung Hwan Jung, Yun Seong Eo, Seung Hoon Kim, Xiao Ying, Hanbyul Choi, Chaerin Hong, Kyungmin Lee, Sung Min Park

Electronic and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

13 Scopus citations

Abstract

A 50-Gb/s differential transimpedance amplifier is realized in a standard 65nm CMOS process, which exploits asymmetric transformer peaking technique for bandwidth extension and employs a modified regulated-cascode input stage with a shunt-feedback common-source amplifier for differential signaling. Measured results demonstrate 52-dBΩ transimpedance gain, 50-GHz bandwidth for 50fF photodiode capacitance, -12.3dBm sensitivity for 10^-12 BER, and 49.2-mW power dissipation from a single 1.2-V supply. To the best of authors' knowledge, this chip achieves the fastest operation speed among the recently reported gigabit CMOS transimpedance amplifiers. The chip occupies the total area of 1.2×0.8mm² including pad.

Original language	English
Title of host publication	2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	357-360
Number of pages	4
ISBN (Electronic)	9781479940905
DOIs	https://doi.org/10.1109/ASSCC.2014.7008934
State	Published - 13 Jan 2015
Event	2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 - Kaohsiung, Taiwan, Province of China Duration: 10 Nov 2014 → 12 Nov 2014

Publication series

Name	2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers

Conference

Conference	2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014
Country/Territory	Taiwan, Province of China
City	Kaohsiung
Period	10/11/14 → 12/11/14

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

Keywords

CMOS
regulated-cascode
TIA
transformer

Access to Document

10.1109/ASSCC.2014.7008934

Cite this

Kim, S. G., Jung, S. H., Eo, Y. S., Kim, S. H., Ying, X., Choi, H., Hong, C., Lee, K., & Park, S. M. (2015). A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology. In 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers (pp. 357-360). Article 7008934 (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2014.7008934

Kim, Sang Gyun ; Jung, Seung Hwan ; Eo, Yun Seong et al. / A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology. 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 357-360 (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers).

@inproceedings{cdcc7936b63448b087a4e1133c801050,

title = "A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology",

abstract = "A 50-Gb/s differential transimpedance amplifier is realized in a standard 65nm CMOS process, which exploits asymmetric transformer peaking technique for bandwidth extension and employs a modified regulated-cascode input stage with a shunt-feedback common-source amplifier for differential signaling. Measured results demonstrate 52-dBΩ transimpedance gain, 50-GHz bandwidth for 50fF photodiode capacitance, -12.3dBm sensitivity for 10-12 BER, and 49.2-mW power dissipation from a single 1.2-V supply. To the best of authors' knowledge, this chip achieves the fastest operation speed among the recently reported gigabit CMOS transimpedance amplifiers. The chip occupies the total area of 1.2×0.8mm2 including pad.",

keywords = "CMOS, regulated-cascode, TIA, transformer",

author = "Kim, {Sang Gyun} and Jung, {Seung Hwan} and Eo, {Yun Seong} and Kim, {Seung Hoon} and Xiao Ying and Hanbyul Choi and Chaerin Hong and Kyungmin Lee and Park, {Sung Min}",

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Kim, SG, Jung, SH, Eo, YS, Kim, SH, Ying, X, Choi, H, Hong, C, Lee, K & Park, SM 2015, A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology. in 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers., 7008934, 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers, Institute of Electrical and Electronics Engineers Inc., pp. 357-360, 2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014, Kaohsiung, Taiwan, Province of China, 10/11/14. https://doi.org/10.1109/ASSCC.2014.7008934

A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology. / Kim, Sang Gyun; Jung, Seung Hwan; Eo, Yun Seong et al.
2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. p. 357-360 7008934 (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Lee, Kyungmin

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N2 - A 50-Gb/s differential transimpedance amplifier is realized in a standard 65nm CMOS process, which exploits asymmetric transformer peaking technique for bandwidth extension and employs a modified regulated-cascode input stage with a shunt-feedback common-source amplifier for differential signaling. Measured results demonstrate 52-dBΩ transimpedance gain, 50-GHz bandwidth for 50fF photodiode capacitance, -12.3dBm sensitivity for 10-12 BER, and 49.2-mW power dissipation from a single 1.2-V supply. To the best of authors' knowledge, this chip achieves the fastest operation speed among the recently reported gigabit CMOS transimpedance amplifiers. The chip occupies the total area of 1.2×0.8mm2 including pad.

AB - A 50-Gb/s differential transimpedance amplifier is realized in a standard 65nm CMOS process, which exploits asymmetric transformer peaking technique for bandwidth extension and employs a modified regulated-cascode input stage with a shunt-feedback common-source amplifier for differential signaling. Measured results demonstrate 52-dBΩ transimpedance gain, 50-GHz bandwidth for 50fF photodiode capacitance, -12.3dBm sensitivity for 10-12 BER, and 49.2-mW power dissipation from a single 1.2-V supply. To the best of authors' knowledge, this chip achieves the fastest operation speed among the recently reported gigabit CMOS transimpedance amplifiers. The chip occupies the total area of 1.2×0.8mm2 including pad.

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Kim SG, Jung SH, Eo YS, Kim SH, Ying X, Choi H et al. A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology. In 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2015. p. 357-360. 7008934. (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers). doi: 10.1109/ASSCC.2014.7008934

A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology

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Bibliographical note

Keywords

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