A 5-Gb/s 2.67-mW/Gb/s digital clock and data recovery with hybrid dithering using a time-dithered delta-sigma modulator

Taeho Lee, Yong Hun Kim, Jaehyeong Sim, Jun Seok Park, Lee Sup Kim

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

A digital clock and data recovery (CDR) employing a time-dithered delta-sigma modulator (TDDSM) is presented. By enabling hybrid dithering of a sampling period as well as an output bit of the TDDSM, the proposed CDR enhances the resolution of digitally controlled oscillator, removes a low-pass filter in the integral path, and reduces jitter generation. Fabricated in a 65-nm CMOS process, the proposed CDR operates at 5-Gb/s data rate with BER <10-12 for PRBS 31. The CDR consumes 13.32 mW at 5 Gb/s and achieves 2.14 and 29.7 ps of a long-term rms and peak-to-peak jitter, respectively.

Original languageEnglish
Article number7163338
Pages (from-to)1450-1459
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume24
Issue number4
DOIs
StatePublished - Apr 2016

Keywords

  • Delta-sigma modulator (DSM)
  • digital clock and data recovery (CDR)
  • digitally controlled oscillator (DCO)
  • high-speed serial link
  • hybrid dithering
  • loop delay
  • resolution
  • time-dithered DSM (TDDSM)

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