A 5-Gb/s 1/8-rate CMOS clock and data recovery circuit

Jin Kyu Kwon, Tae Kwan Heo, Sang Bock Cho, Sung Min Park

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations


A 5-Gb/s clock and data recovery (CDR) circuit, incorporating 625MHz interpolating voltage-controlled oscillators (VCO) and four-phase 1/8-rate phase detectors (PD), is demonstrated. The PD provides linear characteristic that is proportional to the phase difference between the four-phase clocks and the input 5-Gb/s data, and hence produces four-demultiplexed 1.25-Gb/s outputs. The VCO is designed as a four-stage differential ring oscillator, employing the half-rate clock technique so that it can provide 1/8-rate clocks with delay interpolation. Test chips are fabricated in a 0.25μm CMOS technology. The whole chip occupies the area of 1.7×1.4mm2 together with on-chip low pass filters, i.e. two 16pF capacitors and 63kΩ resistors. Post-layout simulations show that the recovered data output exhibits 40ps p-p jitter characteristic for 223 - 1 PRBS serial NRZ input. Chip core dissipates 130mW from a single 2.5V supply.

Original languageEnglish
Pages (from-to)IV-293-IV-296
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - 2004
Event2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada
Duration: 23 May 200426 May 2004


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