A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS

Sang Gyun Kim; Chaerin Hong; Yun Seong Eo; Jihoon Kim; Sung Min Park

doi:10.1109/JSSC.2018.2886323

A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS

Sang Gyun Kim, Chaerin Hong, Yun Seong Eo, Jihoon Kim, Sung Min Park

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

32 Scopus citations

Abstract

This paper presents a fully differential transimpedance amplifier (TIA) realized in a standard 65-nm CMOS process, where a novel mirrored-cascode (MC) input configuration is proposed for differential signaling, i.e., an NMOS cascode amplifier with a resistive feedback for negative output and its MC amplifier via an ac-coupling capacitor for positive output. For bandwidth extension, the third-order asymmetric transformers were carefully employed. Measured results of the proposed MC differential (MCD) TIA demonstrate 54-dB Ω transimpedance gain, 40-GHz bandwidth for 50-fF photodiode capacitance, 19.8-_pA\sqrt \mathrm Hz average noise current spectral density, ±10-ps group delay variation, and 55.2-mW power consumption. Eye diagrams for 32 Gb/s 2¹⁵ -1 pseudo random binary sequence (PRBS) were measured with the input currents of 100-1.5 mApp. The chip occupies the area of 0.6 mm² including I/O pads.

Original language	English
Article number	8594639
Pages (from-to)	1468-1474
Number of pages	7
Journal	IEEE Journal of Solid-State Circuits
Volume	54
Issue number	5
DOIs	https://doi.org/10.1109/JSSC.2018.2886323
State	Published - May 2019

Bibliographical note

Funding Information:
Manuscript received June 8, 2018; revised September 6, 2018; accepted November 28, 2018. Date of publication December 28, 2018; date of current version April 23, 2019. This work was supported by the National Research Foundation of Korea (NRF) Grant through the Korean Government (MSIP) under Grant NRF-2014R1A2A2A01005686. This paper was approved by Guest Editor Azita Emami. (Corresponding author: Sung Min Park.) S. G. Kim and Y. S. Eo are with the Department of Electronic Engineering, Kwangwoon University, Seoul 01897, South Korea.

Publisher Copyright:
© 1966-2012 IEEE.

Keywords

Asymmetric transformers
CMOS
mirrored cascode (MC)
single to differential
transimpedance amplifier (TIA)

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10.1109/JSSC.2018.2886323

Cite this

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title = "A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS",

abstract = "This paper presents a fully differential transimpedance amplifier (TIA) realized in a standard 65-nm CMOS process, where a novel mirrored-cascode (MC) input configuration is proposed for differential signaling, i.e., an NMOS cascode amplifier with a resistive feedback for negative output and its MC amplifier via an ac-coupling capacitor for positive output. For bandwidth extension, the third-order asymmetric transformers were carefully employed. Measured results of the proposed MC differential (MCD) TIA demonstrate 54-dB Ω transimpedance gain, 40-GHz bandwidth for 50-fF photodiode capacitance, 19.8-pA\sqrt \mathrm Hz average noise current spectral density, ±10-ps group delay variation, and 55.2-mW power consumption. Eye diagrams for 32 Gb/s 215 -1 pseudo random binary sequence (PRBS) were measured with the input currents of 100-1.5 mApp. The chip occupies the area of 0.6 mm2 including I/O pads.",

keywords = "Asymmetric transformers, CMOS, mirrored cascode (MC), single to differential, transimpedance amplifier (TIA)",

author = "Kim, {Sang Gyun} and Chaerin Hong and Eo, {Yun Seong} and Jihoon Kim and Park, {Sung Min}",

note = "Funding Information: Manuscript received June 8, 2018; revised September 6, 2018; accepted November 28, 2018. Date of publication December 28, 2018; date of current version April 23, 2019. This work was supported by the National Research Foundation of Korea (NRF) Grant through the Korean Government (MSIP) under Grant NRF-2014R1A2A2A01005686. This paper was approved by Guest Editor Azita Emami. (Corresponding author: Sung Min Park.) S. G. Kim and Y. S. Eo are with the Department of Electronic Engineering, Kwangwoon University, Seoul 01897, South Korea. Publisher Copyright: {\textcopyright} 1966-2012 IEEE.",

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N2 - This paper presents a fully differential transimpedance amplifier (TIA) realized in a standard 65-nm CMOS process, where a novel mirrored-cascode (MC) input configuration is proposed for differential signaling, i.e., an NMOS cascode amplifier with a resistive feedback for negative output and its MC amplifier via an ac-coupling capacitor for positive output. For bandwidth extension, the third-order asymmetric transformers were carefully employed. Measured results of the proposed MC differential (MCD) TIA demonstrate 54-dB Ω transimpedance gain, 40-GHz bandwidth for 50-fF photodiode capacitance, 19.8-pA\sqrt \mathrm Hz average noise current spectral density, ±10-ps group delay variation, and 55.2-mW power consumption. Eye diagrams for 32 Gb/s 215 -1 pseudo random binary sequence (PRBS) were measured with the input currents of 100-1.5 mApp. The chip occupies the area of 0.6 mm2 including I/O pads.

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A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS

Abstract

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Keywords

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