TY - JOUR
T1 - A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS
AU - Kim, Sang Gyun
AU - Hong, Chaerin
AU - Eo, Yun Seong
AU - Kim, Jihoon
AU - Park, Sung Min
N1 - Funding Information:
Manuscript received June 8, 2018; revised September 6, 2018; accepted November 28, 2018. Date of publication December 28, 2018; date of current version April 23, 2019. This work was supported by the National Research Foundation of Korea (NRF) Grant through the Korean Government (MSIP) under Grant NRF-2014R1A2A2A01005686. This paper was approved by Guest Editor Azita Emami. (Corresponding author: Sung Min Park.) S. G. Kim and Y. S. Eo are with the Department of Electronic Engineering, Kwangwoon University, Seoul 01897, South Korea.
Publisher Copyright:
© 1966-2012 IEEE.
PY - 2019/5
Y1 - 2019/5
N2 - This paper presents a fully differential transimpedance amplifier (TIA) realized in a standard 65-nm CMOS process, where a novel mirrored-cascode (MC) input configuration is proposed for differential signaling, i.e., an NMOS cascode amplifier with a resistive feedback for negative output and its MC amplifier via an ac-coupling capacitor for positive output. For bandwidth extension, the third-order asymmetric transformers were carefully employed. Measured results of the proposed MC differential (MCD) TIA demonstrate 54-dB Ω transimpedance gain, 40-GHz bandwidth for 50-fF photodiode capacitance, 19.8-pA\sqrt \mathrm Hz average noise current spectral density, ±10-ps group delay variation, and 55.2-mW power consumption. Eye diagrams for 32 Gb/s 215 -1 pseudo random binary sequence (PRBS) were measured with the input currents of 100-1.5 mApp. The chip occupies the area of 0.6 mm2 including I/O pads.
AB - This paper presents a fully differential transimpedance amplifier (TIA) realized in a standard 65-nm CMOS process, where a novel mirrored-cascode (MC) input configuration is proposed for differential signaling, i.e., an NMOS cascode amplifier with a resistive feedback for negative output and its MC amplifier via an ac-coupling capacitor for positive output. For bandwidth extension, the third-order asymmetric transformers were carefully employed. Measured results of the proposed MC differential (MCD) TIA demonstrate 54-dB Ω transimpedance gain, 40-GHz bandwidth for 50-fF photodiode capacitance, 19.8-pA\sqrt \mathrm Hz average noise current spectral density, ±10-ps group delay variation, and 55.2-mW power consumption. Eye diagrams for 32 Gb/s 215 -1 pseudo random binary sequence (PRBS) were measured with the input currents of 100-1.5 mApp. The chip occupies the area of 0.6 mm2 including I/O pads.
KW - Asymmetric transformers
KW - CMOS
KW - mirrored cascode (MC)
KW - single to differential
KW - transimpedance amplifier (TIA)
UR - http://www.scopus.com/inward/record.url?scp=85064995766&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2018.2886323
DO - 10.1109/JSSC.2018.2886323
M3 - Article
AN - SCOPUS:85064995766
SN - 0018-9200
VL - 54
SP - 1468
EP - 1474
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 5
M1 - 8594639
ER -