A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique

Seong Jun Song, Sung Min Park, Hoi Jun Yoo

Research output: Contribution to journalArticlepeer-review

56 Scopus citations

Abstract

A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-μm standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and a folded differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high common-mode rejection ratio differential amplifier at the ring oscillator output. A 1/8-rate linear phase detector accomplishes the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate the jitter of the recovered clock to be 5.2 ps rms and 47 ps pk-pk for 231 - 1 pseudorandom bit sequence (PRBS) input data. The phase noise is measured to be -112 dBc/Hz at 1-MHz offset. The measured bit error rate is less than 10-6 for 231 - 1 PRBS. The chip excluding output buffers dissipates 70 m\V from a single 2.5-V supply.

Original languageEnglish
Pages (from-to)1213-1219
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Volume38
Issue number7
DOIs
StatePublished - Jul 2003

Keywords

  • 1/8-rate clock
  • Clock and data recovery
  • CMOS
  • Linear phase detector
  • Optical receivers
  • Voltage-controlled oscillator (VCO)

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