A 4-Gb/s clock and data recovery circuit using four-phase 1/8-rate clock

Seong Jun Song, Jaeseo Lee, Sung Min Park, Hoi Jun Yoo

Research output: Contribution to journalConference articlepeer-review


This paper describes a 4-Gb/s clock and data recovery circuit exploiting a four-phase 1/8-rate clock technique for low-power and high-speed operation. The voltage-controlled oscillator with an active inductor load provides the 50% duty-cycle correction operating at 1/8-rate clock. The four-phase detector performing 1:4 DEMUX accomplishes a linear frequency and phase detection with no systematic phase offset. Test chip was fabricated by a 0.25-μm digital CMOS technology. The peak-to-peak jitter of the recovered clock is 47ps for a PRBS of length 231-1. The power dissipation is 70mW with a 2.5-V supply.

Original languageEnglish
Article number1471510
Pages (from-to)239-242
Number of pages4
JournalEuropean Solid-State Circuits Conference
StatePublished - 2002
Event28th European Solid-State Circuits Conference, ESSCIRC 2002 - Florence, Italy
Duration: 24 Sep 200226 Sep 2002


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