A 4-Gb/s clock and data recovery circuit using four-phase 1/8-rate clock

Seong Jun Song; Jaeseo Lee; Sung Min Park; Hoi Jun Yoo

A 4-Gb/s clock and data recovery circuit using four-phase 1/8-rate clock

Seong Jun Song, Jaeseo Lee, Sung Min Park, Hoi Jun Yoo

Electronic and Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

Abstract

This paper describes a 4-Gb/s clock and data recovery circuit exploiting a four-phase 1/8-rate clock technique for low-power and high-speed operation. The voltage-controlled oscillator with an active inductor load provides the 50% duty-cycle correction operating at 1/8-rate clock. The four-phase detector performing 1:4 DEMUX accomplishes a linear frequency and phase detection with no systematic phase offset. Test chip was fabricated by a 0.25-μm digital CMOS technology. The peak-to-peak jitter of the recovered clock is 47ps for a PRBS of length 2³¹-1. The power dissipation is 70mW with a 2.5-V supply.

Original language	English
Article number	1471510
Pages (from-to)	239-242
Number of pages	4
Journal	European Solid-State Circuits Conference
State	Published - 2002
Event	28th European Solid-State Circuits Conference, ESSCIRC 2002 - Florence, Italy Duration: 24 Sep 2002 → 26 Sep 2002

Cite this

@article{ca93f3daff3f4501b7f65640db6e0b1a,

title = "A 4-Gb/s clock and data recovery circuit using four-phase 1/8-rate clock",

abstract = "This paper describes a 4-Gb/s clock and data recovery circuit exploiting a four-phase 1/8-rate clock technique for low-power and high-speed operation. The voltage-controlled oscillator with an active inductor load provides the 50% duty-cycle correction operating at 1/8-rate clock. The four-phase detector performing 1:4 DEMUX accomplishes a linear frequency and phase detection with no systematic phase offset. Test chip was fabricated by a 0.25-μm digital CMOS technology. The peak-to-peak jitter of the recovered clock is 47ps for a PRBS of length 231-1. The power dissipation is 70mW with a 2.5-V supply.",

author = "Song, {Seong Jun} and Jaeseo Lee and Park, {Sung Min} and Yoo, {Hoi Jun}",

year = "2002",

language = "English",

pages = "239--242",

journal = "European Solid-State Circuits Conference",

issn = "1930-8833",

note = "28th European Solid-State Circuits Conference, ESSCIRC 2002 ; Conference date: 24-09-2002 Through 26-09-2002",

}

TY - JOUR

T1 - A 4-Gb/s clock and data recovery circuit using four-phase 1/8-rate clock

AU - Song, Seong Jun

AU - Lee, Jaeseo

AU - Park, Sung Min

AU - Yoo, Hoi Jun

PY - 2002

Y1 - 2002

N2 - This paper describes a 4-Gb/s clock and data recovery circuit exploiting a four-phase 1/8-rate clock technique for low-power and high-speed operation. The voltage-controlled oscillator with an active inductor load provides the 50% duty-cycle correction operating at 1/8-rate clock. The four-phase detector performing 1:4 DEMUX accomplishes a linear frequency and phase detection with no systematic phase offset. Test chip was fabricated by a 0.25-μm digital CMOS technology. The peak-to-peak jitter of the recovered clock is 47ps for a PRBS of length 231-1. The power dissipation is 70mW with a 2.5-V supply.

AB - This paper describes a 4-Gb/s clock and data recovery circuit exploiting a four-phase 1/8-rate clock technique for low-power and high-speed operation. The voltage-controlled oscillator with an active inductor load provides the 50% duty-cycle correction operating at 1/8-rate clock. The four-phase detector performing 1:4 DEMUX accomplishes a linear frequency and phase detection with no systematic phase offset. Test chip was fabricated by a 0.25-μm digital CMOS technology. The peak-to-peak jitter of the recovered clock is 47ps for a PRBS of length 231-1. The power dissipation is 70mW with a 2.5-V supply.

UR - http://www.scopus.com/inward/record.url?scp=84893813479&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:84893813479

SN - 1930-8833

SP - 239

EP - 242

JO - European Solid-State Circuits Conference

JF - European Solid-State Circuits Conference

M1 - 1471510

T2 - 28th European Solid-State Circuits Conference, ESSCIRC 2002

Y2 - 24 September 2002 through 26 September 2002

ER -

A 4-Gb/s clock and data recovery circuit using four-phase 1/8-rate clock

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