A 2.5Gb/s ESD-protected dual-channel optical transceiver array

Jungwon Han; Booyoung Choi; Kangyeob Park; Won Seok Oh; Sung Min Park

doi:10.1109/ASSCC.2007.4425754

A 2.5Gb/s ESD-protected dual-channel optical transceiver array

Jungwon Han, Booyoung Choi, Kangyeob Park, Won Seok Oh, Sung Min Park

Electronic and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

18 Scopus citations

Abstract

This paper describes the design of a dual-channel optical transceiver array realized in a standard 0.18μm CMOS technology for the applications of high-speed digital interface. The transmitter drives a 2-channel VCSEL array at 2.5Gb/s, equipped with the APC (5-15mA) and AMC (4-20mA^pp) loops for constant and reliable optical power outputs. Meanwhile, the receiver exploits the common-gate transimpedance amplifier, demonstrating 87dBΩ transimpedance gain, 1.4GHz bandwidth for 2pF input parasitic capacitance, -18dBm sensitivity for 10^-12 BER, and less than -20dB crosstalk between TX and RX within the bandwidth. The whole 2-channel transceiver array chip dissipates 500mW.

Original language	English
Title of host publication	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Pages	156-159
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2007.4425754
State	Published - 2007
Event	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC - Jeju, Korea, Republic of Duration: 12 Nov 2007 → 14 Nov 2007

Publication series

Name	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Conference

Conference	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Country/Territory	Korea, Republic of
City	Jeju
Period	12/11/07 → 14/11/07

Access to Document

10.1109/ASSCC.2007.4425754

Cite this

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title = "A 2.5Gb/s ESD-protected dual-channel optical transceiver array",

abstract = "This paper describes the design of a dual-channel optical transceiver array realized in a standard 0.18μm CMOS technology for the applications of high-speed digital interface. The transmitter drives a 2-channel VCSEL array at 2.5Gb/s, equipped with the APC (5-15mA) and AMC (4-20mApp) loops for constant and reliable optical power outputs. Meanwhile, the receiver exploits the common-gate transimpedance amplifier, demonstrating 87dBΩ transimpedance gain, 1.4GHz bandwidth for 2pF input parasitic capacitance, -18dBm sensitivity for 10-12 BER, and less than -20dB crosstalk between TX and RX within the bandwidth. The whole 2-channel transceiver array chip dissipates 500mW.",

author = "Jungwon Han and Booyoung Choi and Kangyeob Park and Oh, {Won Seok} and Park, {Sung Min}",

year = "2007",

doi = "10.1109/ASSCC.2007.4425754",

language = "English",

isbn = "1424413605",

series = "2007 IEEE Asian Solid-State Circuits Conference, A-SSCC",

pages = "156--159",

booktitle = "2007 IEEE Asian Solid-State Circuits Conference, A-SSCC",

note = "2007 IEEE Asian Solid-State Circuits Conference, A-SSCC ; Conference date: 12-11-2007 Through 14-11-2007",

}

Han, J, Choi, B, Park, K, Oh, WS & Park, SM 2007, A 2.5Gb/s ESD-protected dual-channel optical transceiver array. in 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC., 4425754, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, pp. 156-159, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, Jeju, Korea, Republic of, 12/11/07. https://doi.org/10.1109/ASSCC.2007.4425754

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AU - Oh, Won Seok

AU - Park, Sung Min

PY - 2007

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N2 - This paper describes the design of a dual-channel optical transceiver array realized in a standard 0.18μm CMOS technology for the applications of high-speed digital interface. The transmitter drives a 2-channel VCSEL array at 2.5Gb/s, equipped with the APC (5-15mA) and AMC (4-20mApp) loops for constant and reliable optical power outputs. Meanwhile, the receiver exploits the common-gate transimpedance amplifier, demonstrating 87dBΩ transimpedance gain, 1.4GHz bandwidth for 2pF input parasitic capacitance, -18dBm sensitivity for 10-12 BER, and less than -20dB crosstalk between TX and RX within the bandwidth. The whole 2-channel transceiver array chip dissipates 500mW.

AB - This paper describes the design of a dual-channel optical transceiver array realized in a standard 0.18μm CMOS technology for the applications of high-speed digital interface. The transmitter drives a 2-channel VCSEL array at 2.5Gb/s, equipped with the APC (5-15mA) and AMC (4-20mApp) loops for constant and reliable optical power outputs. Meanwhile, the receiver exploits the common-gate transimpedance amplifier, demonstrating 87dBΩ transimpedance gain, 1.4GHz bandwidth for 2pF input parasitic capacitance, -18dBm sensitivity for 10-12 BER, and less than -20dB crosstalk between TX and RX within the bandwidth. The whole 2-channel transceiver array chip dissipates 500mW.

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SN - 9781424413607

T3 - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

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BT - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

T2 - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Y2 - 12 November 2007 through 14 November 2007

ER -

A 2.5Gb/s ESD-protected dual-channel optical transceiver array

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