TY - GEN
T1 - A 2.22 Gbps high-throughput NB-LDPC decoder in 65nm CMOS with aggressive overlap scheduling
AU - Choi, Injun
AU - Kim, Ji Hoon
N1 - Funding Information:
This work was supported in part by the Basic Science Research Program through the National Research Foundation of Korea funded by the Ministry of Science, ICT & Future Planning under Grant 2015R1D1A1A01060247 and in part by the IC Design Education Center.
Publisher Copyright:
© 2018 IEEE.
PY - 2018/2/20
Y1 - 2018/2/20
N2 - This paper presents the fully-overlapped non-binary low-density parity-check (NB-LDPC) decoder to improve the throughput performance. The early-bubble (e-bubble) check algorithm and the EVN overlap scheduling is proposed to reduce the iteration latency of the decoder. The proposed decoder for (160, 80) NB-LDPC code over GF(64) achieved a throughput of 2.22 Gbps at a 625-MHz frequency.
AB - This paper presents the fully-overlapped non-binary low-density parity-check (NB-LDPC) decoder to improve the throughput performance. The early-bubble (e-bubble) check algorithm and the EVN overlap scheduling is proposed to reduce the iteration latency of the decoder. The proposed decoder for (160, 80) NB-LDPC code over GF(64) achieved a throughput of 2.22 Gbps at a 625-MHz frequency.
UR - http://www.scopus.com/inward/record.url?scp=85045329020&partnerID=8YFLogxK
U2 - 10.1109/ASPDAC.2018.8297337
DO - 10.1109/ASPDAC.2018.8297337
M3 - Conference contribution
AN - SCOPUS:85045329020
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 315
EP - 316
BT - ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 22 January 2018 through 25 January 2018
ER -