A 2.22 Gbps high-throughput NB-LDPC decoder in 65nm CMOS with aggressive overlap scheduling

Injun Choi; Ji Hoon Kim

doi:10.1109/ASPDAC.2018.8297337

A 2.22 Gbps high-throughput NB-LDPC decoder in 65nm CMOS with aggressive overlap scheduling

Injun Choi, Ji Hoon Kim

Electronic and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents the fully-overlapped non-binary low-density parity-check (NB-LDPC) decoder to improve the throughput performance. The early-bubble (e-bubble) check algorithm and the EVN overlap scheduling is proposed to reduce the iteration latency of the decoder. The proposed decoder for (160, 80) NB-LDPC code over GF(64) achieved a throughput of 2.22 Gbps at a 625-MHz frequency.

Original language	English
Title of host publication	ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	315-316
Number of pages	2
ISBN (Electronic)	9781509006021
DOIs	https://doi.org/10.1109/ASPDAC.2018.8297337
State	Published - 20 Feb 2018
Event	23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018 - Jeju, Korea, Republic of Duration: 22 Jan 2018 → 25 Jan 2018

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	2018-January

Conference

Conference	23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018
Country/Territory	Korea, Republic of
City	Jeju
Period	22/01/18 → 25/01/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

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10.1109/ASPDAC.2018.8297337

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Choi, I., & Kim, J. H. (2018). A 2.22 Gbps high-throughput NB-LDPC decoder in 65nm CMOS with aggressive overlap scheduling. In ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings (pp. 315-316). (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2018-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2018.8297337

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title = "A 2.22 Gbps high-throughput NB-LDPC decoder in 65nm CMOS with aggressive overlap scheduling",

abstract = "This paper presents the fully-overlapped non-binary low-density parity-check (NB-LDPC) decoder to improve the throughput performance. The early-bubble (e-bubble) check algorithm and the EVN overlap scheduling is proposed to reduce the iteration latency of the decoder. The proposed decoder for (160, 80) NB-LDPC code over GF(64) achieved a throughput of 2.22 Gbps at a 625-MHz frequency.",

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Choi, I & Kim, JH 2018, A 2.22 Gbps high-throughput NB-LDPC decoder in 65nm CMOS with aggressive overlap scheduling. in ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 315-316, 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea, Republic of, 22/01/18. https://doi.org/10.1109/ASPDAC.2018.8297337

A 2.22 Gbps high-throughput NB-LDPC decoder in 65nm CMOS with aggressive overlap scheduling. / Choi, Injun; Kim, Ji Hoon.
ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 315-316 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2018-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper presents the fully-overlapped non-binary low-density parity-check (NB-LDPC) decoder to improve the throughput performance. The early-bubble (e-bubble) check algorithm and the EVN overlap scheduling is proposed to reduce the iteration latency of the decoder. The proposed decoder for (160, 80) NB-LDPC code over GF(64) achieved a throughput of 2.22 Gbps at a 625-MHz frequency.

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Choi I, Kim JH. A 2.22 Gbps high-throughput NB-LDPC decoder in 65nm CMOS with aggressive overlap scheduling. In ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. p. 315-316. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1109/ASPDAC.2018.8297337

A 2.22 Gbps high-throughput NB-LDPC decoder in 65nm CMOS with aggressive overlap scheduling

Abstract

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