A 2144.2-bits/min/mW 5-Heterogeneous PE-based Domain-Specific Reconfigurable Array Processor for 8-Ch Wearable Brain-Computer Interface SoC

Wooseok Byun, Minkyu Je, Ji Hoon Kim

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This paper proposes a reconfigurable array processor (RAP) based wearable brain-computer interface (BCI) SoC that can energy-efficiently accelerate linear algebra operations mainly required for target identification algorithms in visual-stimuli-based BCI. The proposed domain-specific RAP contains an array of dynamically reconfigurable and scalable processing-elements for energy efficiency, and supports almost all three levels of basic linear algebra subprograms (BLAS) as well as matrix decompositions. In addition, this work proposes an optimized target identification (TI) algorithm for RAP, which leads to a higher information transfer rate (ITR) of 139.9-bits/min and a better accuracy of 95.4% compared to the previous work [5], and a processing energy efficiency in ITR of 2144.2-bits/min/mW. This SoC was fabricated in 130nm CMOS and, with the proposed TI algorithm, it shows 16.8x energy efficiency compared to the state-of-the-art [1].

Original languageEnglish
Title of host publication2021 Symposium on VLSI Circuits, VLSI Circuits 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9784863487796
DOIs
StatePublished - 13 Jun 2021
Event35th Symposium on VLSI Circuits, VLSI Circuits 2021 - Virutal, Online
Duration: 13 Jun 202119 Jun 2021

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume2021-June

Conference

Conference35th Symposium on VLSI Circuits, VLSI Circuits 2021
CityVirutal, Online
Period13/06/2119/06/21

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