TY - GEN
T1 - A 2144.2-bits/min/mW 5-Heterogeneous PE-based Domain-Specific Reconfigurable Array Processor for 8-Ch Wearable Brain-Computer Interface SoC
AU - Byun, Wooseok
AU - Je, Minkyu
AU - Kim, Ji Hoon
N1 - Funding Information:
Acknowledgements This work was supported in part by the NRF of Korea under Grant 2017M3C7A1028859 and in part by the IDEC. References [1] V. Kartsch, TBioCAS '19. [2] D. Shin, TCAS-I '18. [3] C-H. Wu, TCAS-I '19. [4] G. Peng, JSSC '20. [5] W. Byun, A-SSCC '19. [6] M. Shabany, JSSC '13. [7] M. Nakanishi, PLoS ONE '15.
Publisher Copyright:
© 2021 JSAP.
PY - 2021/6/13
Y1 - 2021/6/13
N2 - This paper proposes a reconfigurable array processor (RAP) based wearable brain-computer interface (BCI) SoC that can energy-efficiently accelerate linear algebra operations mainly required for target identification algorithms in visual-stimuli-based BCI. The proposed domain-specific RAP contains an array of dynamically reconfigurable and scalable processing-elements for energy efficiency, and supports almost all three levels of basic linear algebra subprograms (BLAS) as well as matrix decompositions. In addition, this work proposes an optimized target identification (TI) algorithm for RAP, which leads to a higher information transfer rate (ITR) of 139.9-bits/min and a better accuracy of 95.4% compared to the previous work [5], and a processing energy efficiency in ITR of 2144.2-bits/min/mW. This SoC was fabricated in 130nm CMOS and, with the proposed TI algorithm, it shows 16.8x energy efficiency compared to the state-of-the-art [1].
AB - This paper proposes a reconfigurable array processor (RAP) based wearable brain-computer interface (BCI) SoC that can energy-efficiently accelerate linear algebra operations mainly required for target identification algorithms in visual-stimuli-based BCI. The proposed domain-specific RAP contains an array of dynamically reconfigurable and scalable processing-elements for energy efficiency, and supports almost all three levels of basic linear algebra subprograms (BLAS) as well as matrix decompositions. In addition, this work proposes an optimized target identification (TI) algorithm for RAP, which leads to a higher information transfer rate (ITR) of 139.9-bits/min and a better accuracy of 95.4% compared to the previous work [5], and a processing energy efficiency in ITR of 2144.2-bits/min/mW. This SoC was fabricated in 130nm CMOS and, with the proposed TI algorithm, it shows 16.8x energy efficiency compared to the state-of-the-art [1].
UR - http://www.scopus.com/inward/record.url?scp=85111879276&partnerID=8YFLogxK
U2 - 10.23919/VLSICircuits52068.2021.9492405
DO - 10.23919/VLSICircuits52068.2021.9492405
M3 - Conference contribution
AN - SCOPUS:85111879276
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
BT - 2021 Symposium on VLSI Circuits, VLSI Circuits 2021
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 13 June 2021 through 19 June 2021
ER -
