A 208-MHz, 0.75-mW Self-Calibrated Reference Frequency Quadrupler for a 2-GHz Fractional-N Ring-PLL in 4-nm FinFET CMOS

Kyungmin Lee, Jaehong Jung, Seungjin Kim, Seunghyun Oh, Jongwoo Lee, Sung Min Park

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

This brief presents a 208-MHz, 0.75-mW self-calibrated reference frequency quadrupler (RFQ), which provides a 4x higher reference clock with minimal deterministic frequency error. The digital-assisted calibration technique is exploited to compensate wide range of frequency and duty cycle errors and to reduce the noise degradation of analog calibration loop. Also, instead of utilizing a duty cycle corrector for 2x clock, reusing a delay cell reduces the power consumption by 50%. The fractional-N ring-PLL with the proposed RFQ was implemented in a 4nm FinFET CMOS process. The active area of the RFQ is 0.0175mm2 while the whole PLL occupies the area of 0.109mm2. By using the RFQ, the measured RMS-jitter of the PLL is definitely improved from 6.6ps to 3.35ps at 1.92GHz output frequency.

Original languageEnglish
Pages (from-to)2719-2723
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume70
Issue number8
DOIs
StatePublished - 1 Aug 2023

Bibliographical note

Publisher Copyright:
© 2004-2012 IEEE.

Keywords

  • Clock multiplier
  • delay control
  • duty-cycle correction (DCC)
  • phase-locked loop (PLL)
  • reference frequency doubler
  • reference frequency quadrupler

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