Abstract
This paper presents a 208-MHz, 0.75-mW selfcalibrated reference frequency quadrupler (RFQ), which provides a 4x higher reference clock with minimal deterministic frequency error. The digital-assisted calibration technique is exploited to compensate wide range of frequency and duty cycle errors and to reduce the noise degradation of analog calibration loop. Also, instead of utilizing a duty cycle corrector for 2x clock, reusing a delay cell reduces the power consumption by 50%. The fractional-N ring-PLL with the proposed RFQ was implemented in a 4nm FinFET CMOS process. The active area of the RFQ is 0.0175mm2 while the whole PLL occupies the area of 0.109mm2. By using the RFQ, the measured RMS-jitter of the PLL is definitely improved from 6.6ps to 3.35ps at 1.92GHz output frequency.
Original language | English |
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Pages (from-to) | 1 |
Number of pages | 1 |
Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
DOIs | |
State | Accepted/In press - 2022 |
Keywords
- Calibration
- clock multiplier
- Clocks
- Computer architecture
- delay control
- Delays
- duty-cycle correction (DCC)
- Microprocessors
- Phase locked loops
- phase-locked loop (PLL)
- Power demand
- reference frequency doubler
- reference frequency quadrupler