A 20-Gb/s transformer-based current-mode optical receiver in 0.13- μm CMOS

Jungwon Han; Booyoung Choi; Mikyung Seo; Jisook Yun; Dongmyung Lee; Taewook Kim; Yunseong Eo; Sung Min Park

doi:10.1109/TCSII.2010.2047309

A 20-Gb/s transformer-based current-mode optical receiver in 0.13- μm CMOS

Jungwon Han, Booyoung Choi, Mikyung Seo, Jisook Yun, Dongmyung Lee, Taewook Kim, Yunseong Eo, Sung Min Park

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

31 Scopus citations

Abstract

A 20-Gb/s current-mode optical receiver is realized in a 0.13-μm CMOS process, which consists of a common-gate transimpedance amplifier (TIA) with on-chip transformers, a six-stage postamplifier (PA) with an offset cancellation network, and an output buffer. The transformer-based inductive peaking technique is exploited in the TIA to isolate the parasitic capacitances at high-impedance nodes and, hence, to enlarge the bandwidth. The PA incorporates source degeneration and interleaving active feedback techniques to achieve wide bandwidth and flat frequency response so as not to degrade the operation speed of the whole optical receiver. Measured results demonstrate 60-dBΩ transimpedance gain, 12.6-GHz bandwidth even with 0.4-pF large input parasitic capacitance, -13-dBm sensitivity for a 10^-12 bit error rate, and 38.3-mW power consumption from a single 1.2-V supply.

Original language	English
Article number	5466056
Pages (from-to)	348-352
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	57
Issue number	5
DOIs	https://doi.org/10.1109/TCSII.2010.2047309
State	Published - May 2010

Keywords

CMOS
Current mode
High speed
Optical receivers
Shunt-double-series peaking
Transformer

Access to Document

10.1109/TCSII.2010.2047309

Cite this

@article{2649823efe7043fc8d6cf3681d2ffa91,

title = "A 20-Gb/s transformer-based current-mode optical receiver in 0.13- μm CMOS",

abstract = "A 20-Gb/s current-mode optical receiver is realized in a 0.13-μm CMOS process, which consists of a common-gate transimpedance amplifier (TIA) with on-chip transformers, a six-stage postamplifier (PA) with an offset cancellation network, and an output buffer. The transformer-based inductive peaking technique is exploited in the TIA to isolate the parasitic capacitances at high-impedance nodes and, hence, to enlarge the bandwidth. The PA incorporates source degeneration and interleaving active feedback techniques to achieve wide bandwidth and flat frequency response so as not to degrade the operation speed of the whole optical receiver. Measured results demonstrate 60-dBΩ transimpedance gain, 12.6-GHz bandwidth even with 0.4-pF large input parasitic capacitance, -13-dBm sensitivity for a 10-12 bit error rate, and 38.3-mW power consumption from a single 1.2-V supply.",

keywords = "CMOS, Current mode, High speed, Optical receivers, Shunt-double-series peaking, Transformer",

author = "Jungwon Han and Booyoung Choi and Mikyung Seo and Jisook Yun and Dongmyung Lee and Taewook Kim and Yunseong Eo and Park, {Sung Min}",

note = "Funding Information: Manuscript received October 30, 2009; revised February 9, 2010; accepted March 8, 2010. Date of current version May 14, 2010. This work was supported in part by the Ministry of Education, Science and Technology, Korean Government, under Korea Science and Engineering Foundation Grant 2009063084 and in part by Seoul R&BD Program (NT080509). This paper was recommended by Associate Editor V. Stojanovic.",

year = "2010",

month = may,

doi = "10.1109/TCSII.2010.2047309",

language = "English",

volume = "57",

pages = "348--352",

journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",

issn = "1549-7747",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "5",

}

TY - JOUR

T1 - A 20-Gb/s transformer-based current-mode optical receiver in 0.13- μm CMOS

AU - Han, Jungwon

AU - Choi, Booyoung

AU - Seo, Mikyung

AU - Yun, Jisook

AU - Lee, Dongmyung

AU - Kim, Taewook

AU - Eo, Yunseong

AU - Park, Sung Min

N1 - Funding Information: Manuscript received October 30, 2009; revised February 9, 2010; accepted March 8, 2010. Date of current version May 14, 2010. This work was supported in part by the Ministry of Education, Science and Technology, Korean Government, under Korea Science and Engineering Foundation Grant 2009063084 and in part by Seoul R&BD Program (NT080509). This paper was recommended by Associate Editor V. Stojanovic.

PY - 2010/5

Y1 - 2010/5

N2 - A 20-Gb/s current-mode optical receiver is realized in a 0.13-μm CMOS process, which consists of a common-gate transimpedance amplifier (TIA) with on-chip transformers, a six-stage postamplifier (PA) with an offset cancellation network, and an output buffer. The transformer-based inductive peaking technique is exploited in the TIA to isolate the parasitic capacitances at high-impedance nodes and, hence, to enlarge the bandwidth. The PA incorporates source degeneration and interleaving active feedback techniques to achieve wide bandwidth and flat frequency response so as not to degrade the operation speed of the whole optical receiver. Measured results demonstrate 60-dBΩ transimpedance gain, 12.6-GHz bandwidth even with 0.4-pF large input parasitic capacitance, -13-dBm sensitivity for a 10-12 bit error rate, and 38.3-mW power consumption from a single 1.2-V supply.

AB - A 20-Gb/s current-mode optical receiver is realized in a 0.13-μm CMOS process, which consists of a common-gate transimpedance amplifier (TIA) with on-chip transformers, a six-stage postamplifier (PA) with an offset cancellation network, and an output buffer. The transformer-based inductive peaking technique is exploited in the TIA to isolate the parasitic capacitances at high-impedance nodes and, hence, to enlarge the bandwidth. The PA incorporates source degeneration and interleaving active feedback techniques to achieve wide bandwidth and flat frequency response so as not to degrade the operation speed of the whole optical receiver. Measured results demonstrate 60-dBΩ transimpedance gain, 12.6-GHz bandwidth even with 0.4-pF large input parasitic capacitance, -13-dBm sensitivity for a 10-12 bit error rate, and 38.3-mW power consumption from a single 1.2-V supply.

KW - CMOS

KW - Current mode

KW - High speed

KW - Optical receivers

KW - Shunt-double-series peaking

KW - Transformer

UR - http://www.scopus.com/inward/record.url?scp=77952708011&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2010.2047309

DO - 10.1109/TCSII.2010.2047309

M3 - Article

AN - SCOPUS:77952708011

SN - 1549-7747

VL - 57

SP - 348

EP - 352

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 5

M1 - 5466056

ER -

A 20-Gb/s transformer-based current-mode optical receiver in 0.13- μm CMOS

Abstract

Keywords

Access to Document

Fingerprint

Cite this