A 2-stage low noise amplifier in 90 nm CMOS for 2.4 GHz applications

Hyun Myung Oh; Jae Sun Kim; Bang Chul Jung; Ji Hoon Kim; Hyoungho Ko; Chul Young Kim

doi:10.1166/asl.2016.7917

A 2-stage low noise amplifier in 90 nm CMOS for 2.4 GHz applications

Hyun Myung Oh
, Jae Sun Kim
, Bang Chul Jung
, Ji Hoon Kim
, Hyoungho Ko
, Chul Young Kim

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

In this paper, a 2-stage low noise amplifier (LNA) is implemented in a 90 nm CMOS technology for 2.4 GHz applications. The measurement results show a noise figure of 3.2 dB with a gain 19.9 dB. The circuit consumes 6 mA from a 1.2 V supply, and has 7.2 mW power consumption. The core size is 1.1 mm × 0.95 mm and the chip size including pads is 1.34 mm × 1 mm.

Original language	English
Pages (from-to)	3228-3231
Number of pages	4
Journal	Advanced Science Letters
Volume	22
Issue number	11
DOIs	https://doi.org/10.1166/asl.2016.7917
State	Published - Nov 2016

Bibliographical note

Publisher Copyright:
© 2016 American Scientific Publishers. All rights reserved.

Keywords

2.4 GHz
CMOS
LNA

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10.1166/asl.2016.7917

Cite this

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title = "A 2-stage low noise amplifier in 90 nm CMOS for 2.4 GHz applications",

abstract = "In this paper, a 2-stage low noise amplifier (LNA) is implemented in a 90 nm CMOS technology for 2.4 GHz applications. The measurement results show a noise figure of 3.2 dB with a gain 19.9 dB. The circuit consumes 6 mA from a 1.2 V supply, and has 7.2 mW power consumption. The core size is 1.1 mm × 0.95 mm and the chip size including pads is 1.34 mm × 1 mm.",

keywords = "2.4 GHz, CMOS, LNA",

author = "Oh, \{Hyun Myung\} and Kim, \{Jae Sun\} and Jung, \{Bang Chul\} and Kim, \{Ji Hoon\} and Hyoungho Ko and Kim, \{Chul Young\}",

year = "2016",

month = nov,

doi = "10.1166/asl.2016.7917",

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AU - Ko, Hyoungho

AU - Kim, Chul Young

PY - 2016/11

Y1 - 2016/11

N2 - In this paper, a 2-stage low noise amplifier (LNA) is implemented in a 90 nm CMOS technology for 2.4 GHz applications. The measurement results show a noise figure of 3.2 dB with a gain 19.9 dB. The circuit consumes 6 mA from a 1.2 V supply, and has 7.2 mW power consumption. The core size is 1.1 mm × 0.95 mm and the chip size including pads is 1.34 mm × 1 mm.

AB - In this paper, a 2-stage low noise amplifier (LNA) is implemented in a 90 nm CMOS technology for 2.4 GHz applications. The measurement results show a noise figure of 3.2 dB with a gain 19.9 dB. The circuit consumes 6 mA from a 1.2 V supply, and has 7.2 mW power consumption. The core size is 1.1 mm × 0.95 mm and the chip size including pads is 1.34 mm × 1 mm.

KW - 2.4 GHz

KW - CMOS

KW - LNA

UR - https://www.scopus.com/pages/publications/85013395229

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M3 - Article

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JF - Advanced Science Letters

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ER -

A 2-stage low noise amplifier in 90 nm CMOS for 2.4 GHz applications

Abstract

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Keywords

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