A 2-bit recessed channel nonvolatile memory device with a lifted charge-trapping node

Jang Gn Yun, Il Han Park, Seongjae Cho, Jung Hoon Lee, Doo Hyun Kim, Gil Sung Lee, Yoon Kim, Jong Duk Lee, Byung Gook Park

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


A novel 2-bit recessed channel nonvolatile memory device is proposed in this paper. Physically separated two charge-trapping nodes are lifted up to achieve large sensing margin in highly scaled memory devices. A successful 2-bit/cell operation with effective suppression of second bit effect is achieved by adopting the lifted charge-trapping node scheme. In addition, the effect of the source/drain junction depth on memory operation characteristics is investigated.

Original languageEnglish
Article number4633648
Pages (from-to)111-115
Number of pages5
JournalIEEE Transactions on Nanotechnology
Issue number1
StatePublished - Jan 2009

Bibliographical note

Funding Information:
Manuscript received June 27, 2007; revised October 15, 2007 and December 6, 2007; accepted September 8, 2008. First published September 26, 2008; current version published January 16, 2009. This work was supported by Samsung Electronics under Project “The Research on Structure and Characteristics of the Nonvolatile Memory Devices.” The review of this paper was arranged by Associate Editor B. Yu.


  • 2-bit nonvolatile memory device
  • Lifted charge-trapping node scheme
  • Recessed channel structure
  • Second bit effect (SBE)


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