A 1.5 Gbps transceiver chipset in 0.13-μm CMOS for serial digital interface

Kyungmin Lee, Seung Hoon Kim, Sung Min Park

Research output: Contribution to journalArticlepeer-review

Abstract

This paper presents a transceiver chipset realized in a 0.13-mm CMOS technology for serial digital interface of video data transmission, which compensates the electrical cable loss of 45 dB in maximum at 1.5 Gbps. For the purpose, the TX equips pre-emphasis in the main driver by utilizing a D-FF with clocks generated from a wide-range tuning PLL. In RX, two-stage continuous-time linear equalizers and a limiting amplifier are exploited as a front-end followed by a 1/8-rate CDR to retime the data with inherent 1:8 demultiplexing function. Measured results demonstrate data recovery from 270 Mbps to 1.5 Gbps. The TX consumes 104 mW from 1.2/3.3-V supplies and occupies the area of 1.485 mm2, whereas the RX dissipate 133 mW from a 1.2-V supply and occupies the area of 1.44 mm2.

Original languageEnglish
Pages (from-to)552-560
Number of pages9
JournalJournal of Semiconductor Technology and Science
Volume17
Issue number4
DOIs
StatePublished - Aug 2017

Keywords

  • CMOS
  • Digital interface
  • Equalization
  • Pre-emphasis
  • Receiver
  • Serial links
  • Transmitter

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