A 1.2V 5.2mW 40dB 2.5Gb/s limiting amplifier in 0.18μm CMOS using negative-impedance compensation

Kwisung Yoo; Dongmyung Lee; Gunhee Han; Sung Min Park; Won Seok Oh

doi:10.1109/ISSCC.2007.373585

A 1.2V 5.2mW 40dB 2.5Gb/s limiting amplifier in 0.18μm CMOS using negative-impedance compensation

Kwisung Yoo, Dongmyung Lee, Gunhee Han, Sung Min Park, Won Seok Oh

Electronic and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

17 Scopus citations

Abstract

A 2.5Gb/s limiting amplifier is realized in a standard 0.18μm CMOS process, exploiting the negative-impedance compensation technique. Measurements show 2.5Gb/s operation (0.5pF ESD protection diodes included) with 40dB gain, 21ps_rms jitter for 2^S1-1 PRBS, 9.5mV_pp input sensitivity with BER <10^-12, and 5.2mW power dissipation from a 1.2V supply. The chip core occupies 0.25×0.1mm².

Original language	English
Title of host publication	2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	56-57
Number of pages	2
ISBN (Print)	1424408539, 9781424408535
DOIs	https://doi.org/10.1109/ISSCC.2007.373585
State	Published - 2007
Event	54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States Duration: 11 Feb 2007 → 15 Feb 2007

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)	0193-6530

Conference

Conference	54th IEEE International Solid-State Circuits Conference, ISSCC 2007
Country/Territory	United States
City	San Francisco, CA
Period	11/02/07 → 15/02/07

Access to Document

10.1109/ISSCC.2007.373585

Cite this

Yoo, K., Lee, D., Han, G., Park, S. M., & Oh, W. S. (2007). A 1.2V 5.2mW 40dB 2.5Gb/s limiting amplifier in 0.18μm CMOS using negative-impedance compensation. In 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers (pp. 56-57). Article 4242262 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2007.373585

Yoo, Kwisung ; Lee, Dongmyung ; Han, Gunhee et al. / A 1.2V 5.2mW 40dB 2.5Gb/s limiting amplifier in 0.18μm CMOS using negative-impedance compensation. 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2007. pp. 56-57 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

@inproceedings{d447b6729eff459fa6ceb1b9028186cd,

title = "A 1.2V 5.2mW 40dB 2.5Gb/s limiting amplifier in 0.18μm CMOS using negative-impedance compensation",

abstract = "A 2.5Gb/s limiting amplifier is realized in a standard 0.18μm CMOS process, exploiting the negative-impedance compensation technique. Measurements show 2.5Gb/s operation (0.5pF ESD protection diodes included) with 40dB gain, 21psrms jitter for 2S1-1 PRBS, 9.5mVpp input sensitivity with BER <10-12, and 5.2mW power dissipation from a 1.2V supply. The chip core occupies 0.25×0.1mm2.",

author = "Kwisung Yoo and Dongmyung Lee and Gunhee Han and Park, {Sung Min} and Oh, {Won Seok}",

year = "2007",

doi = "10.1109/ISSCC.2007.373585",

language = "English",

isbn = "1424408539",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "56--57",

booktitle = "2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers",

note = "54th IEEE International Solid-State Circuits Conference, ISSCC 2007 ; Conference date: 11-02-2007 Through 15-02-2007",

}

Yoo, K, Lee, D, Han, G, Park, SM & Oh, WS 2007, A 1.2V 5.2mW 40dB 2.5Gb/s limiting amplifier in 0.18μm CMOS using negative-impedance compensation. in 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers., 4242262, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 56-57, 54th IEEE International Solid-State Circuits Conference, ISSCC 2007, San Francisco, CA, United States, 11/02/07. https://doi.org/10.1109/ISSCC.2007.373585

A 1.2V 5.2mW 40dB 2.5Gb/s limiting amplifier in 0.18μm CMOS using negative-impedance compensation. / Yoo, Kwisung; Lee, Dongmyung; Han, Gunhee et al.
2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2007. p. 56-57 4242262 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - A 2.5Gb/s limiting amplifier is realized in a standard 0.18μm CMOS process, exploiting the negative-impedance compensation technique. Measurements show 2.5Gb/s operation (0.5pF ESD protection diodes included) with 40dB gain, 21psrms jitter for 2S1-1 PRBS, 9.5mVpp input sensitivity with BER <10-12, and 5.2mW power dissipation from a 1.2V supply. The chip core occupies 0.25×0.1mm2.

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Yoo K, Lee D, Han G, Park SM, Oh WS. A 1.2V 5.2mW 40dB 2.5Gb/s limiting amplifier in 0.18μm CMOS using negative-impedance compensation. In 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2007. p. 56-57. 4242262. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2007.373585

A 1.2V 5.2mW 40dB 2.5Gb/s limiting amplifier in 0.18μm CMOS using negative-impedance compensation

Abstract

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