TY - GEN
T1 - A 1.2V 5.2mW 40dB 2.5Gb/s limiting amplifier in 0.18μm CMOS using negative-impedance compensation
AU - Yoo, Kwisung
AU - Lee, Dongmyung
AU - Han, Gunhee
AU - Park, Sung Min
AU - Oh, Won Seok
PY - 2007
Y1 - 2007
N2 - A 2.5Gb/s limiting amplifier is realized in a standard 0.18μm CMOS process, exploiting the negative-impedance compensation technique. Measurements show 2.5Gb/s operation (0.5pF ESD protection diodes included) with 40dB gain, 21psrms jitter for 2S1-1 PRBS, 9.5mVpp input sensitivity with BER <10-12, and 5.2mW power dissipation from a 1.2V supply. The chip core occupies 0.25×0.1mm2.
AB - A 2.5Gb/s limiting amplifier is realized in a standard 0.18μm CMOS process, exploiting the negative-impedance compensation technique. Measurements show 2.5Gb/s operation (0.5pF ESD protection diodes included) with 40dB gain, 21psrms jitter for 2S1-1 PRBS, 9.5mVpp input sensitivity with BER <10-12, and 5.2mW power dissipation from a 1.2V supply. The chip core occupies 0.25×0.1mm2.
UR - http://www.scopus.com/inward/record.url?scp=34548849100&partnerID=8YFLogxK
U2 - 10.1109/ISSCC.2007.373585
DO - 10.1109/ISSCC.2007.373585
M3 - Conference contribution
AN - SCOPUS:34548849100
SN - 1424408539
SN - 9781424408535
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 56
EP - 57
BT - 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 54th IEEE International Solid-State Circuits Conference, ISSCC 2007
Y2 - 11 February 2007 through 15 February 2007
ER -