TY - GEN
T1 - A 110.3-bits/min 8-ch ssvep-based brain-computer interface soc with 87.9% accuracy
AU - Byun, Wooseok
AU - Kirn, Dokyun
AU - Kiin, Sung Yeon
AU - Kim, Ji Hoon
N1 - Publisher Copyright:
© IEEE 2019
PY - 2019/11
Y1 - 2019/11
N2 - A wearable brain-computer interface (BCI) based on steady-state visual evoked potential (SSVEP) has been widely studied to enable paralyzed patients to communicate with others. However, target identification accuracy and information transfer rate (JLTK), which are general performance indicators of SSVEP- based BCI system, still need to be further improved in wearable devices. This paper proposes 8-channel SSVEP-based visual target identification system-on-chip (SoC) to improve the ITR of low-cost wearable BCI device while dramatically reducing the computational complexity without accuracy degradation. The proposed target identification algorithm, CCA-CR, includes algorithmic optimizations and candidate reduction (CR) method that reduce signal processing load by at least 75% without degrading target identification accuracy and ITR. This paper also proposes a matrix decomposition processor (MDP) that calculates complex matrix arithmetic operations through systolic array based CCA-CR engines. Compared to the state-of-the-art CCA-based algorithm, the proposed SoC implemented in FPGA exhibits 63% better ITR with 33% reduction of recording time without accuracy degradation.
AB - A wearable brain-computer interface (BCI) based on steady-state visual evoked potential (SSVEP) has been widely studied to enable paralyzed patients to communicate with others. However, target identification accuracy and information transfer rate (JLTK), which are general performance indicators of SSVEP- based BCI system, still need to be further improved in wearable devices. This paper proposes 8-channel SSVEP-based visual target identification system-on-chip (SoC) to improve the ITR of low-cost wearable BCI device while dramatically reducing the computational complexity without accuracy degradation. The proposed target identification algorithm, CCA-CR, includes algorithmic optimizations and candidate reduction (CR) method that reduce signal processing load by at least 75% without degrading target identification accuracy and ITR. This paper also proposes a matrix decomposition processor (MDP) that calculates complex matrix arithmetic operations through systolic array based CCA-CR engines. Compared to the state-of-the-art CCA-based algorithm, the proposed SoC implemented in FPGA exhibits 63% better ITR with 33% reduction of recording time without accuracy degradation.
KW - Brain-computer interface (bci)
KW - Canonical correlation analysis (cca)
KW - Matrix decomposition
KW - Steady-state visual evoked potential (ssvep)
KW - System-on-chip
KW - Target identification
UR - http://www.scopus.com/inward/record.url?scp=85108251736&partnerID=8YFLogxK
U2 - 10.1109/A-SSCC47793.2019.9056983
DO - 10.1109/A-SSCC47793.2019.9056983
M3 - Conference contribution
AN - SCOPUS:85108251736
T3 - Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
SP - 201
EP - 204
BT - Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Y2 - 4 November 2019 through 6 November 2019
ER -