A 110.3-bits/min 8-ch ssvep-based brain-computer interface soc with 87.9% accuracy

Wooseok Byun; Dokyun Kirn; Sung Yeon Kiin; Ji Hoon Kim

doi:10.1109/A-SSCC47793.2019.9056983

A 110.3-bits/min 8-ch ssvep-based brain-computer interface soc with 87.9% accuracy

Wooseok Byun, Dokyun Kirn, Sung Yeon Kiin, Ji Hoon Kim

Electronic and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

A wearable brain-computer interface (BCI) based on steady-state visual evoked potential (SSVEP) has been widely studied to enable paralyzed patients to communicate with others. However, target identification accuracy and information transfer rate (JLTK), which are general performance indicators of SSVEP- based BCI system, still need to be further improved in wearable devices. This paper proposes 8-channel SSVEP-based visual target identification system-on-chip (SoC) to improve the ITR of low-cost wearable BCI device while dramatically reducing the computational complexity without accuracy degradation. The proposed target identification algorithm, CCA-CR, includes algorithmic optimizations and candidate reduction (CR) method that reduce signal processing load by at least 75% without degrading target identification accuracy and ITR. This paper also proposes a matrix decomposition processor (MDP) that calculates complex matrix arithmetic operations through systolic array based CCA-CR engines. Compared to the state-of-the-art CCA-based algorithm, the proposed SoC implemented in FPGA exhibits 63% better ITR with 33% reduction of recording time without accuracy degradation.

Original language	English
Title of host publication	Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	201-204
Number of pages	4
ISBN (Electronic)	9781728151069
DOIs	https://doi.org/10.1109/A-SSCC47793.2019.9056983
State	Published - Nov 2019
Event	15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 - Macao, China Duration: 4 Nov 2019 → 6 Nov 2019

Publication series

Name	Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Volume	2019-November

Conference

Conference	15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Country/Territory	China
City	Macao
Period	4/11/19 → 6/11/19

Bibliographical note

Publisher Copyright:
© IEEE 2019

Keywords

Brain-computer interface (bci)
Canonical correlation analysis (cca)
Matrix decomposition
Steady-state visual evoked potential (ssvep)
System-on-chip
Target identification

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10.1109/A-SSCC47793.2019.9056983

Cite this

Byun, W., Kirn, D., Kiin, S. Y., & Kim, J. H. (2019). A 110.3-bits/min 8-ch ssvep-based brain-computer interface soc with 87.9% accuracy. In Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 (pp. 201-204). Article 9056983 (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019; Vol. 2019-November). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/A-SSCC47793.2019.9056983

@inproceedings{99f02282d45b40d4a23e104d65427a9d,

title = "A 110.3-bits/min 8-ch ssvep-based brain-computer interface soc with 87.9% accuracy",

abstract = "A wearable brain-computer interface (BCI) based on steady-state visual evoked potential (SSVEP) has been widely studied to enable paralyzed patients to communicate with others. However, target identification accuracy and information transfer rate (JLTK), which are general performance indicators of SSVEP- based BCI system, still need to be further improved in wearable devices. This paper proposes 8-channel SSVEP-based visual target identification system-on-chip (SoC) to improve the ITR of low-cost wearable BCI device while dramatically reducing the computational complexity without accuracy degradation. The proposed target identification algorithm, CCA-CR, includes algorithmic optimizations and candidate reduction (CR) method that reduce signal processing load by at least 75% without degrading target identification accuracy and ITR. This paper also proposes a matrix decomposition processor (MDP) that calculates complex matrix arithmetic operations through systolic array based CCA-CR engines. Compared to the state-of-the-art CCA-based algorithm, the proposed SoC implemented in FPGA exhibits 63% better ITR with 33% reduction of recording time without accuracy degradation.",

keywords = "Brain-computer interface (bci), Canonical correlation analysis (cca), Matrix decomposition, Steady-state visual evoked potential (ssvep), System-on-chip, Target identification",

author = "Wooseok Byun and Dokyun Kirn and Kiin, {Sung Yeon} and Kim, {Ji Hoon}",

note = "Publisher Copyright: {\textcopyright} IEEE 2019; 15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 ; Conference date: 04-11-2019 Through 06-11-2019",

year = "2019",

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doi = "10.1109/A-SSCC47793.2019.9056983",

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series = "Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019",

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Byun, W, Kirn, D, Kiin, SY & Kim, JH 2019, A 110.3-bits/min 8-ch ssvep-based brain-computer interface soc with 87.9% accuracy. in Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019., 9056983, Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, vol. 2019-November, Institute of Electrical and Electronics Engineers Inc., pp. 201-204, 15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, Macao, China, 4/11/19. https://doi.org/10.1109/A-SSCC47793.2019.9056983

A 110.3-bits/min 8-ch ssvep-based brain-computer interface soc with 87.9% accuracy. / Byun, Wooseok; Kirn, Dokyun; Kiin, Sung Yeon et al.
Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 201-204 9056983 (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019; Vol. 2019-November).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - A wearable brain-computer interface (BCI) based on steady-state visual evoked potential (SSVEP) has been widely studied to enable paralyzed patients to communicate with others. However, target identification accuracy and information transfer rate (JLTK), which are general performance indicators of SSVEP- based BCI system, still need to be further improved in wearable devices. This paper proposes 8-channel SSVEP-based visual target identification system-on-chip (SoC) to improve the ITR of low-cost wearable BCI device while dramatically reducing the computational complexity without accuracy degradation. The proposed target identification algorithm, CCA-CR, includes algorithmic optimizations and candidate reduction (CR) method that reduce signal processing load by at least 75% without degrading target identification accuracy and ITR. This paper also proposes a matrix decomposition processor (MDP) that calculates complex matrix arithmetic operations through systolic array based CCA-CR engines. Compared to the state-of-the-art CCA-based algorithm, the proposed SoC implemented in FPGA exhibits 63% better ITR with 33% reduction of recording time without accuracy degradation.

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Byun W, Kirn D, Kiin SY, Kim JH. A 110.3-bits/min 8-ch ssvep-based brain-computer interface soc with 87.9% accuracy. In Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 201-204. 9056983. (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019). doi: 10.1109/A-SSCC47793.2019.9056983

A 110.3-bits/min 8-ch ssvep-based brain-computer interface soc with 87.9% accuracy

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access to Document

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