Abstract
A wideband Internet of Things (IoT) transmitter (TX) employing open-loop binary frequency-shift keying (BFSK) modulator with a pseudo-randomized phase transition (PRPT) time and a single-supply Class-G harmonic rejection (HR) power amplifier (PA) is presented. The proposed open-loop phase switching modulator eliminates the data-rate limitation in a conventional phase-locked loop (PLL)-based closed-loop modulator, while the PRPT scheme increases the effective phase resolution with a better power efficiency than delta-sigma modulation (DSM)-based randomization. Thus, a low spur level below -40 dBc is achieved with only a 4-bit phase resolution. The Class-G HR PA, including a four-level supply voltage waveform generator, is proposed as a high-efficiency and low spurious PA architecture. The proposed HR PA presents the third- and fifth-harmonics cancellation over the 0.3-to-1-GHz band, while only a single supply is required for Class-G implementation of the HR PA. The proposed BFSK TX is implemented in a 55-nm CMOS process. Measured with a 0.3-to-1-GHz continuous-wave carrier, TX output power and PA drain efficiency are 2.7 ± 0.2 dB and 52% ± 3%, respectively, operating from a 0.9-V supply. The HRs of -31.4/-42.7 and -28.2/-42.4 dBc at the third/fifth harmonics are measured at the lowest (0.3 GHz) and the highest (1 GHz) carrier frequencies, respectively. With a data rate of 1 Mb/s, the measured FSK errors are 3.6% and 4.2% at both ends of the operating frequency.
| Original language | English |
|---|---|
| Pages (from-to) | 892-905 |
| Number of pages | 14 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 57 |
| Issue number | 3 |
| DOIs | |
| State | Published - 1 Mar 2022 |
Bibliographical note
Publisher Copyright:© 1966-2012 IEEE.
Keywords
- Binary frequency-shift keying (BFSK)
- Class-G
- CMOS
- harmonic rejection (HR)
- low power
- power amplifier (PA)
- transmitter (TX)