A 0.13 μm CMOS UWB Radar Receiver Front-end with Differential Error-correction and Feedback Gain via Back-to-back Regeneration and Bandwidth Staggering

This work proposes an ultra-wideband (UWB) radar receiver front-end implemented with a low cost 0.13 μm CMOS technology. The proposed receiver front-end is a cascaded configuration of a low-noise amplifier (LNA) with single-differential conversion and a two-stage radio frequency variable gain amplifier (RFVGA) to ensure a sufficient signal strength and quality over the various radar reception distance. The LNA is constructed with noisecancelling common gate (CG)-common source (CS) amplifier for wideband input matching and single-todifferential conversion. Two-stage RFVGA successively corrects the differential gain and phase imbalance and provides regenerated gain by the back-to-back inverters employed at the cascode and output node of each stage. The frequency response of LNA and RFVGA are staggered. Subsequently, the broadband spectrum of 6-to-9 GHz are covered with low pass response of LNA, high-pass and bandpass response of each VGA stages. Simulation results show that the maximum and minimum voltage gains are 26 dB and 13 dB, respectively, while consuming only 12 mW of power from a 1.2 V supply. The prototype circuit operates at a minimum noise figure (NF) of 8.72 dB and a third-order intercept point (IIP3) of 8.4 dBm.