In this paper, we present a new fast Fourier transform (FFT) algorithm to reduce the table size of twiddle factors required in pipelined FFT processing. The proposed algorithm can reduce the table size to half, compared to the radix-22 algorithm, while retaining the simple structure. In addition, a new dynamic data scaling approach is presented to reduce hardware complexity without degrading signal-to- quantization-noise ratio (SQNR). To verify the proposed algorithm, a 2048-point pipelined FFT processor is designed using a 0.18 μm CMOS process. By combining the proposed algorithm and the radix-22 algorithm, the table size is reduced to 35% and 53% compared to the radix-2 and radix-22 algorithms, respectively. The FFT processor occupies 1.95 mm2 and achieves SQNR of more than 55 dB without increasing the internal wordlength progressively using the proposed dynamic data scaling.
|Journal||Advanced Science Letters|
|State||Published - Nov 2016|
- Data scaling
- FFT (Fast Fourier Transform)
- Pipelined processing