1T DRAM with Raised SiGe Quantum Well for Sensing Margin Improvement

Si Won Lee, Seongjae Cho, Il Hwan Cho, Garam Kim

Research output: Contribution to journalArticlepeer-review


In this paper, a novel one-transistor dynamic random-access memory (1T DRAM) with a raised SiGe quantum well (QW) under one gate in the double-gate (DG) structure is proposed. The proposed structure can improve the poor performance of the retention time and sensing margin which is the problem of the conventional 1T DRAM. In write operation, the performance is improved through the band to band tunneling (BTBT) between body and drain and through valence band offset between SiGe and Si. Also by utilizing the physical barrier of oxide, read “1” retention time can be increased. The fabrication process is also proposed.

Original languageEnglish
Pages (from-to)64-70
Number of pages7
JournalJournal of Semiconductor Technology and Science
Issue number1
StatePublished - Feb 2023

Bibliographical note

Publisher Copyright:
© 2023, Institute of Electronics Engineers of Korea. All rights reserved.


  • One-transistor (1T) dynamic random-access memory (DRAM)
  • sensing margin
  • technology computer-aided design (TCAD)


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